Progressive insertion placement of elements on an integrated cir

Details Progressive insertion placement of elements on an integrated cir Progressive insertion placement of elements on an integrated cir

1985-11-21

1988-06-28

Lall, Parshotam S.

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364488, G06F 1560

Patent

active

047544082

ABSTRACT:
A method of placing circuit elements in an integrated circuit. The chip area is divided into a grid. In an initial pass, the elements are randomly placed in the grid locations, and these placements are recorded. Thereafter, the elements are sequentially replaced in each of the grid locations, and a score is calculated for the wiring interconnections to the remaining elements as they were last recorded. The placement yielding the best score is recorded for that element. This placement is repeated for each of the elements. Once all the elements have been replaced, a final score is compared with the last best score. If the recent final score is better, the placements associated with that score are saved as the best placements. Then the process of replacement is repeated until a given number of iterations fails to yield a better score.

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IBM Technical Disclosure Bulletin, vol. 13, No. 1, Jun., 1970, pp. 274-276, T. C. Raymond.
IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar., 1974, pp. 3121-3125, W. E. Donath.
IBM Burlington Technical Bulletin, TR 19.90024, "A System for Automatic Layout of Gate Array Chips", Sep. 1981, Lallier, Hickson and Jackson.

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