Programming verification method of nonvolatile memory cell,...

Details Programming verification method of nonvolatile memory cell,... Programming verification method of nonvolatile memory cell,...

2007-01-30

2007-01-30

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

10848236

ABSTRACT:
A programming verification method of verifying programming of a nonvolatile memory cell, the method comprising at least the steps of: selecting first, second, . . . and n-th references corresponding to first, second, . . . and n-th threshold voltages specifying lower limit values of states1, 2, . . . and n, respectively; applying a programming voltage to the nonvolatile memory cell; sensing a threshold voltage level of the nonvolatile memory cell; comparing the sensed threshold voltage level with the first reference to output a first result; comparing the threshold voltage level with one of the second and third references selected according to the first result to output a second result; and comparing the first and second results with an expectation value and, in the case where the first and second results are equal to the expectation value, indicating that the programming has succeeded, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

REFERENCES:
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5675537 (1997-10-01), Bill et al.
patent: 5838041 (1998-11-01), Sakagami et al.
patent: 6529405 (2003-03-01), Chang
patent: 2004/0233727 (2004-11-01), Iwase et al.
patent: 5-81072 (1993-11-01), None
patent: 5-304277 (1993-11-01), None
patent: 9-116119 (1997-05-01), None
patent: 2001-156188 (2001-06-01), None
patent: 2001-156189 (2001-06-01), None
patent: 2001-230332 (2001-08-01), None
patent: 2002-190535 (2002-07-01), None

Affiliated with

Also associated with

Rating

Programming verification method of nonvolatile memory cell,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programming verification method of nonvolatile memory cell,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming verification method of nonvolatile memory cell,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3734951