Programming thermal test chip arrays

Details Programming thermal test chip arrays Programming thermal test chip arrays

2000-12-13

2003-05-06

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090, C324S758010

Reexamination Certificate

active

06559667

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit testing, and more particularly, to the testing of the thermal characteristics of a semiconductor package.
DESCRIPTION OF RELATED ART
The testing of a package containing integrated circuits has become more complicated and important as the current densities increase. High operating temperatures will shorten the lifetime of a semiconductor device. In performing thermal testing, conventional methodology uses a dummy device to supply power and read temperature off the device. Typically, a certain amount of current is put through the dummy device to change the temperature of the device. The temperature is read by a diode or other temperature sensor that is calibrated and reacts in a linear manner with temperature changes.
One concern with such methodology using dummy devices is that the actual emulated devices are very complex, making it difficult to perform a test that accurately emulates the thermal signature of the actual device. In the prior art, this problem is attempted to be overcome by using arrays of smaller dies that are formed to simulate a production die. For example, assume that a microprocessor die is 300 mils×300 mils. A thermal test die may be made of a number of smaller test dies having dimensions of 50×50 mils. Hence, a 6×6 array of smaller test dies is formed that will emulate the larger production die.
A single thermal test chip, such as provided in the prior art, is depicted in FIG.
1
. This thermal test chip is 100 mils on each side and includes a heating element, such as a resistive heating element
12
, and a sensing element, such as a diode
14
. The power to the resistive heating element
12
is provided by leads
16
at one edge of the die
10
. Similarly, forward biasing signals are provided at leads
18
of the die
10
.
The thermal test chips
10
are assembled into an array, in the prior art, such as that depicted in
FIG. 2
, which shows a 5×5 array. One of the concerns with such an array
20
is that only the exterior thermal test chips
10
are accessible to provide power for heating the resistive elements
12
or the forward biasing voltages to the diode
14
. Hence, there is no access to the thermal test chips in the middle of the array, indicated by the shaded squares in FIG.
2
. This inability to access any of the individual chips
10
reduces the accuracy and testability of a thermal test chip array. Furthermore, it was not possible to individually activate selected ones of the thermals test chips within the middle of the array, reducing accuracy of emulation.
One method of overcoming some of these limitations is to perform “stitch bonding” of the individual thermal test chips to one another. This required a complicated chip bonding technique and the wire bonds are of higher resistance than the metal traces that extend through the test chips
10
. Therefore, there is a voltage drop caused by the mismatch in resistances between the wire bonds and the traces and an error would be created in the temperature readings. Hence, there was no continuous connection of the thermal test chip arrays that would provide access to the internal test chips within the array.
SUMMARY OF THE INVENTION
There is a need for a thermal test chip arrangement which provides modularity in allowing a plurality of test chips to be formed into an array of selected dimensions, yet provides access to internal test chips in the array without requiring connection techniques such as stitch bonding.
These and other needs are met by embodiments of the present invention which provide a thermal test chip arrangement comprising a plurality of thermal test chips arranged in an array, each thermal test chip having a heating circuit and a temperature sensing circuit. A first set of conductive lines traverse unbroken across the array with the heating circuit of each thermal test chip being connected to some of the first set of conductive lines. The first set of conductive lines provides power to the thermal test chips. A second set of conductive lines traverse unbroken across the entire array with the temperature sensing circuit of each thermal test chip being connected to some of the second set of conductive lines. The second set of conductive lines carries power to the temperature sensing circuits of the thermal testing chips.
By providing conductive lines which traverse unbroken across the entire array of thermal test chips, a metallization method by which any chip in a multiple array of thermal test chips can be addressed to supply heating power or temperature sensors, is produced. This allows conditional selecting of thermal test chips, increasing the accuracy and testability, as well as the flexibility of the emulation by the thermal test chip.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


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