Programming process for 3-level programming logic devices

Details Programming process for 3-level programming logic devices Programming process for 3-level programming logic devices

1993-05-04

1994-09-20

Bowler, Alyssa H.

Boots, shoes, and leggings

364718, 364735, 3647505, 364258, 364DIG1, 307465, G06F 9302

Patent

active

053496914

ABSTRACT:
A process of programming a programmable logic device (PLD) to carry out a specified logic function. The PLD contains three levels of logic implemented as a plurality of functional blocks, each with AND and OR planes, and a programmable interconnect matrix or logic expander carrying out AND logic. After providing such a PLD with specified size constraints and after specifying a logic function, the function is split or factored into subfunctions or factors. A Boolean factorization procedure chooses factors by replacing pairs of product terms in the first factor with their supercube and minimizing the number input terms and product terms required. Subfunctions or factors which are too large can be simplified by combining pairs of inputs in the interconnect matrix. The product terms of a subfunction or factor can be ordered according to the number of input terms they have and assigned to the functional blocks one at a time. Functional blocks which use many inputs or product terms per output can have some of their assigned subfunctions split so as to pack the PLD more densely. Split subfunctions or factors are recombined in the interconnect matrix. After assigning terms to functional blocks and the matrix, they are loaded into the PLD using a device programmer to configure the logic arrays in the PLD.

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