Programming of semiconductor read only memory

Details Programming of semiconductor read only memory Programming of semiconductor read only memory

1978-06-12

1980-06-17

Hecker, Stuart N.

Static information storage and retrieval

Read only systems

Semiconductive

G11C 1700

Patent

active

042087260

ABSTRACT:
A semiconductor integrated circuit is shown in the form of an MOS read only memory or ROM formed by standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, output lines are metal strips, and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by the presence or absence of a contact between an output metal line and an N+ drain region of a transistor, or by the presence or absence of a moat forming the transistor of the cell. In moat programming, if both cells in a pair are programmed as zeros, then both contact and moat are eliminated, thus reducing capacitive loading and increasing speed. In contact programming, the moat can be removed for inactive bits to reduce loading.

REFERENCES:
patent: 3618050 (1971-11-01), Heeren
Baitinger et al., IGFET Read-Only Memory, IBM Tech. Disc. Bul., vol. 14, No. 5, 10/71, pp. 1429-1430.
Chu et al., Conversion of Read/Write Memory to Read-Only Memory, IBM Tech. Disc. Bul., vol. 17, No. 9, 2/75, pp. 2586-2587.
Platt, Read/Write to Read-Only Memory Conversion, IBM Tech. Disc. Bul., vol. 17, No. 12, 5/75, p.3543.
Balasubramanian et al., Two Device Per Bit, Precharged ROS with Differential Sensing, IBM Tech. Disc. Bul., vol. 19, No. 1, 6/76.

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