Programming of nonvolatile memory cells

Details Programming of nonvolatile memory cells Programming of nonvolatile memory cells

2002-05-28

2004-12-07

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185280

Reexamination Certificate

active

06829172

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electrically erasable, programmable read only memory (EEPROM) cells and specifically, to methods for programming thereto.
BACKGROUND OF THE INVENTION
FIG. 1
, to which reference is made, illustrates a typical prior art floating gate cell, comprising two diffusion areas, source
102
and drain
104
, embedded in a substrate
105
, between which is a channel
100
. A floating gate
101
is located above but insulated from channel
100
, and a gate
112
is located above but insulated from floating gate
101
.
Typically, when programming the floating gate cell, programming voltages V
G
and V
D
are applied to gate
112
and drain
104
, respectively, and a low source voltage V
S
is applied to source
102
. For array applications, a row of gates are formed into a word line, and a column of drain and source are formed into bit lines along which voltages V
D
and V
S
, respectively, are supplied.
The source and drain voltages V
S
and V
D
, respectively, create a lateral field that pulls channel electrons from source
102
to drain
104
. This is indicated by arrow
10
. Near drain
104
, a vertical field created by the gate voltage V
G
allows hot channel electrons to be injected (arrow
12
) into floating gate
101
. Once injected into floating gate
101
, the electrons are distributed equally across the entire gate, increasing the threshold voltage V
TH
of floating gate
101
.
Another type of non-volatile cell is the nitride, read only memory (NROM) cell, described in Applicant's copending U.S. patent application Ser. No. 08/905,286, entitled “Two Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” which was filed Aug. 1, 1997. The disclosure of the above-identified application is incorporated herein by reference.
Similar to the floating gate cell of
FIG. 1
, the NROM cell illustrated in
FIGS. 2A and 2B
, to which reference is now made, has channel
100
between two diffusion areas
102
and
104
. However, unlike the floating gate cell, the NROM cell has two separated and separately chargeable areas
106
and
108
. Each chargeable area defines one bit. For the dual bit cell of
FIG. 2
, the separately chargeable areas
106
and
108
are found within a nitride layer
110
formed in an oxide-nitride-oxide (ONO) sandwich (layers
109
,
110
and
111
) underneath gate
112
.
To program the left bit in area
106
, the left diffusion area
102
receives the high programming voltage V
D
(i.e. area
102
is the drain) and right diffusion area
104
is grounded (i.e. area
104
is the source). Hence the electrons flow from area
104
to area
102
. This is indicated by arrow
114
. The channel hot electrons are then injected into the nitride layer, in area
106
. The negative charge in area
106
raises the threshold voltage of the cell, if read in the reverse direction.
The opposite is true for programming area
108
; the left diffusion area
102
is the source (i.e. grounded) and right diffusion area
104
is the drain (i.e. receives high programming voltage V
D
). The cell is therefore programmed in the opposite direction, as indicated by arrow
113
, and the electrons then jump up into chargeable area
108
.
For NROM cells, each bit is read in the direction opposite (a “reverse read”) to that of its programming direction. An explanation of the reverse read process is described in U.S. patent application Ser. No. 08/905,286, mentioned above. Thus, to read the left bit stored in area
106
, right diffusion area
104
is the drain and left diffusion area
102
is the source. This is known as the “read through” direction, indicated by arrow
113
. To read the right bit stored in area
108
, the cell is read in the opposite direction, indicated by arrow
114
. Thus, left diffusion area
102
is the drain and right diffusion area
104
is the source.
During the read operation, the presence of the gate and drain voltages V
G
and V
D
, respectively, induce a depletion layer
54
(
FIG. 2B
) and an inversion layer
52
in the center of channel
100
. The drain voltage V
D
is large enough to induce a depletion region
55
near drain
104
which extends to the depletion layer
54
of channel
100
. This is known as “barrier lowering” and it causes “punch-through” of electrons from the inversion layer
52
to the drain
104
.
Since area
106
is near left diffusion area
102
which, for this case, acts as the source (i.e. low voltage level), the charge state of area
106
will determine whether or not the inversion layer
52
is extended to the source
102
. If enough electrons are trapped in left area
106
, then the voltage thereacross will not be sufficient to extend inversion layer
52
to the source
102
, the cell's current will be low, and a “0” will be read. The opposite is true if area
106
has no charge.
Reference is now made to
FIGS. 3A
,
3
B and
3
C, which are timing diagrams of an exemplary prior art programming schedule for NROM cells. Typically, when programming an NROM cell, programming pulses
120
A,
120
B and
120
C, consisting of programming voltages V
D
, V
S
, and V
G
, respectively, are applied to the cell. Programming pulses
120
are then followed by program verify pulses
122
A,
122
B and
122
C, consisting of read voltages V
D
, V
S
, and V
G
, respectively, during which time the cell is read.
If there are enough electrons trapped in the bit, a “0” is read, and the cell is verified as programmed. If, however, during the read operation, the inversion layer is not strong enough to prevent the current flow through the channel, than the bit will be read as a “1”, and the cell will fail program verification.
The sequence of pulses
120
and
122
are repeatedly applied until the effect of the charged trapped in area
106
(or
108
) has reached the desired level and the cell is considered “programmed”. The programming process is then terminated.
Due to ever demanding manufacturing requirements, the semiconductor industry is continuously searching for ways to improve the programming process. There exist two contradicting programming requirements; 1) to increase the programming speed, thereby reducing the cost of testing the part, and 2) to improve the control of the final programmed threshold, thereby enhancing product reliability.
The first requirement can easily be met just by increasing the drain and gate potentials to their maximum values. However, this strategy will not meet the second requirement due to many process and environmental parameters that affect the programming rate and its variations.
To achieve the second requirement, there are two basic options, controlling the length of the programming sequence, and/or stepping the amplitude of the gate voltage potential.
The article “Nonvolatile Multilevel Memories for Digital Applications”, published in the
IEEE Magazine
on Dec. 12, 1998, discusses a number of proposed methods for programming multi-level floating gate circuits, including that of controlling the programming time length. One such method is discussed In the section
Programming and Accuracy,
2)
Drain Voltage Programming,
as follows: 1) a constant gate voltage is set, 2) per bit level of the multi-level cell, a constant drain voltage is determined, and 3) the cell is programmed for a predetermined time period. At the completion of the time period, the programming is terminated. Alternately, the article describes an approach whereby after each programming pulse, the threshold voltage V
TH
is verified. Upon reaching the target threshold voltage, programming is terminated.
U.S. Pat. No. 5,523,972 describes a floating gate method that entails incrementally increasing the programming gate voltage V
G
, while keeping other factors constant (e.g. source and drain voltages, V
S
and V
D
, respectively). In the described programming algorithm, each cell is checked to determine whether or not it has reached the desired state. If not, a programming gate voltage pulse of a slightly higher voltage is ap

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