Programming of memory cells using connected floating gate analog

Details Programming of memory cells using connected floating gate analog Programming of memory cells using connected floating gate analog

1997-12-16

1999-01-12

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518522, 3651851, G11C 1606

Patent

active

058597964

ABSTRACT:
A reference cell (114) has a "floating gate" (116) that is tied to a voltage reference (118) in emulation of a programmed cell. An associated programming method is used which compares the voltage of a node (112) associated with the cell (114) with the voltage on a similar node (108) associated with a selected cell (12) in the array; the array cell (12) is determined to be sufficiently programmed when a predetermined relationship is obtained between these two nodes. In this manner, a separate verify mode is avoided.

REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5293560 (1994-03-01), Harari
patent: 5528546 (1996-06-01), Chao et al.
patent: 5579274 (1996-11-01), Van Buskirk et al.
patent: 5629892 (1997-05-01), Tang
patent: 5684741 (1997-11-01), Talreja

Affiliated with

Also associated with

Rating

Programming of memory cells using connected floating gate analog does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programming of memory cells using connected floating gate analog, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming of memory cells using connected floating gate analog will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1521827