Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2005-04-22
2009-10-13
Nguyen, Phu K (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S502000, C345S520000
Reexamination Certificate
active
07602395
ABSTRACT:
Multiple graphics devices are operable in parallel to render stereo images using efficient programming techniques. The same command stream is delivered to each graphics device, and device masks are used to control the execution of commands by different graphics devices. A viewing transform command corresponding to a left-eye transform is executed by one device while a viewing transform command corresponding to a right-eye transform is executed another device. Other rendering commands are executed by both devices to render the same image from somewhat different viewpoints.
REFERENCES:
patent: 4449201 (1984-05-01), Clark
patent: 5321810 (1994-06-01), Case et al.
patent: 5598525 (1997-01-01), Nally et al.
patent: 5664163 (1997-09-01), Yutaka et al.
patent: 5790130 (1998-08-01), Gannett
patent: 5794016 (1998-08-01), Kelleher
patent: 5841444 (1998-11-01), Mun
patent: 6023381 (2000-02-01), Grigor et al.
patent: 6049859 (2000-04-01), Gliese et al.
patent: 6078339 (2000-06-01), Meinerth et al.
patent: 6166748 (2000-12-01), Van Hook et al.
patent: 6191800 (2001-02-01), Arenburg et al.
patent: 6259461 (2001-07-01), Brown
patent: 6317133 (2001-11-01), Root et al.
patent: 6362818 (2002-03-01), Gardiner et al.
patent: 6445391 (2002-09-01), Sowizral et al.
patent: 6469746 (2002-10-01), Maida
patent: 6473086 (2002-10-01), Morein et al.
patent: 6570571 (2003-05-01), Morzumi
patent: 6724390 (2004-04-01), Dragony et al.
patent: 6747654 (2004-06-01), Laksono et al.
patent: 6781590 (2004-08-01), Katsura et al.
patent: 6844879 (2005-01-01), Miyauchi
patent: 2003/0016223 (2003-01-01), Miyauchi
patent: 2003/0086601 (2003-05-01), Lee et al.
patent: 2003/0128216 (2003-07-01), Walls et al.
patent: 2004/0075623 (2004-04-01), Hartman
patent: 2005/0012749 (2005-01-01), Gonzalez
patent: 2005/0088445 (2005-04-01), Gonzalez
patent: 0571969 (2003-05-01), None
Whitman, “Dynamic Load Balancing For Parallel Polygon Rendering” IEEE Computer Graphics and Applications, IEEE Inc. New York, U.S. vol. 14, No. 4, pp. 41-48, Jul. 1, 1994.
Nguyen Phu K
NVIDIA Corporation
Townsend and Townsend / and Crew LLP
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