Programming method of multilevel memories and corresponding...

Details Programming method of multilevel memories and corresponding... Programming method of multilevel memories and corresponding...

2008-01-08

2008-01-08

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189110, C365S230060

Reexamination Certificate

active

07317637

ABSTRACT:
A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

REFERENCES:
patent: 5661685 (1997-08-01), Lee et al.
patent: 2001/0040825 (2001-11-01), Sugimura
patent: 2002/0024846 (2002-02-01), Kawahara et al.
patent: 2003/0151945 (2003-08-01), Tanzawa
patent: 2003/0206469 (2003-11-01), Wong

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