Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-09-19
2003-07-01
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06587381
ABSTRACT:
Japanese Patent Application No. 2001-137165, filed May 8, 2001, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to a programming method for a non-volatile semiconductor memory device formed from twin memory cells each being equipped with one word gate and two non-volatile memory elements controlled by two control gates.
BACKGROUND
There is known a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) type non-volatile semiconductor device in which a gate dielectric layer between a channel and a gate is formed from a stacked body including a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charge is trapped in the silicon nitride film.
A MONOS-type non-volatile semiconductor memory device is described in a reference (Y. Hayashi, et al., 2000 Symposium on VLSI Technology, Digest of Technical Papers, p. 122-p. 123). The reference describes a twin MONOS flash memory cell equipped with one word gate and two non-volatile memory elements (MONOS memory elements or cells) controlled by two control gates. In other words, one flash memory cell includes two charge trap sites.
A plurality of twin MONOS flash memory cells each having the structure described above are arranged in the row direction and the column direction in multiple rows and columns to form a memory cell array region.
Two bit lines, one word line, and two control gate lines are required to drive a MONOS flash memory cell. However, when driving a plurality of twin memory cells, these lines can be commonly connected for different control gates if they are set at the same potential.
Operations of this type of flash memory include erasing, programming, and reading data. Normally, data programming or data reading is performed at selected cells (selected non-volatile memory elements) in units of 8 bits or 16 bits simultaneously.
It is noted that, in the MONOS flash memory, a plurality of twin MONOS flash memory cells that are not mutually isolated are connected to one word line. For programming data at a specified selected cell, not only must the voltage of a twin MONOS flash memory including the selected cell be appropriately set, but also the voltage of an adjacent twin MONOS flash memory cell must be appropriately set.
It is noted that the non-volatile memory of the type described above experiences a problem of data disturbance. The data disturb means disturbance of data at an unselected cell (unselected non-volatile memory element). When a selected cell is programmed by applying a high voltage to the control gate line and the bit line for the selected cell, the high voltage is also applied to the unselected cell due to the commonly shared wiring. When this situation is repeated for each programming, data disturbance occurs; in other words, the unselected cell is programmed or its data is erased.
SUMMARY
Therefore, it is an object of the present invention to provide a programming method for a non-volatile semiconductor memory device, in which, when data is programmed at a selected cell, voltages are appropriately set for a twin memory cell including the selected cell and an adjacent twin memory cell to thereby prevent disturbance at unselected cells.
In accordance with one embodiment of the present invention, a programming method in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−1), (i), and (i+1) whose word gates are connected to one word line, data for the second non-volatile memory element of the twin memory cell (i) is programmed, comprises:
setting the word line to a programming word line selection voltage;
setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to a programming control gate voltage;
setting the second control gate of the twin memory cell (i−1) and the first control gate of the twin memory cell (i) to an over-ride voltage;
setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i) and the first non-volatile memory element of the twin memory cell (i+1) to a programming bit line voltage; and
setting a bit line connected to the second non-volatile memory element of the twin memory cell (i+1) to a voltage higher than 0 V.
In accordance with another embodiment of the present invention, a programming method in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−1), (i), and (i+1) whose word gates are connected to one word line, data for the first non-volatile memory element of the twin memory cell (i) is programmed, comprises:
setting the word line to a programming word line selection voltage;
setting the second control gate of the twin memory cell (i−1) and the first control gate of the twin memory cell (i) to a programming control gate voltage;
setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to an over-ride voltage;
setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i−1) and the first non-volatile memory element of the twin memory cell (i) to a programming bit line voltage; and
setting a bit line connected to the first non-volatile memory element of the twin memory cell (i−1) to a voltage higher than 0 V.
In both of the embodiments described above, a potential difference between a source and a drain (bit lines) of an unselected twin memory cell adjacent to a selected cell (selected non-volatile memory element) in which data is programmed is made smaller, thus preventing punch-through current at the unselected twin memory cell, such that disturbance at the unselected cell (unselected non-volatile memory element) can be prevented.
Also, the voltage higher than 0 volt that is set at the bit line may preferably be equal to or greater than the programming word line selection voltage. As a result, a transistor section including the word gate in a unselected twin memory cell adjacent to a selected cell is difficult to turn on, such that the flow of punch-through current is prevented. As a result, this too prevents disturbance from occurring at the unselected cell adjacent to the selected cell.
Also, in both of the embodiments described above, current that flows in the bit line during programming is restricted by the constant current source, such that the voltage for the bit line can be properly set and the programming operation can be securely performed.
It is noted that the programming word line selection voltage may preferably be set to a voltage that is high enough to be able to cause a current greater than a current provided by the constant current source to flow between a source and a drain of the selected twin memory cell. As a result, the current that flows in the bit line during programming is also restricted at a constant level by the constant current source, such that the voltage for the bit line can be properly set and the programming operation can be securely performed.
As described above, when the programming word line selection voltage is set at a high level, disturbance at an unselected cell readily occurs. However, a potential difference between a source and a drain of a unselected cell is reduced as described above, and disturbance at the unselected cell can be prevented,
Each of the first and second non-volatile memory elements may include an ONO film formed from an oxide film (O), a nitride film (N) and an oxide film (O), which can be used as a charge trap site, but can have any other structure without being restricted to the structure described above.
REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5414693 (1995-05-01), Ma et al.
patent: 5422504 (1995-06-01), Ch
Kamei Teruhiko
Kanai Masahiro
Halo LSI Design & Device Technology, Inc.
Nguyen Tan T.
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