Programming circuit for programmable logic array I/O cell

Details Programming circuit for programmable logic array I/O cell Programming circuit for programmable logic array I/O cell

1987-04-14

1988-11-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307363, 307468, 307592, 307605, H03K 19177

Patent

active

047836067

ABSTRACT:
An improved architecture for programming an output cell (macro cell) in a PLD. The memory cells for the macro cell are stored in the main array itself. Upon power-up, a power-on sense circuit senses the presence of power and enables an architecture portion of the main array while disabling the rest of the main array. The power-on sense signal also enables a path from the output of the array to the macro cell elements to be programmed. When the power-on sense signal is removed a short time after power-up, this path is blocked so that the array outputs continue on their normal path and the architecture portion of the array is disabled while the rest of the array is enabled for normal operation.

REFERENCES:
patent: 4458163 (1984-07-01), Wheeler et al.
patent: 4609838 (1986-09-01), Huang
patent: 4625129 (1986-11-01), Ueno
patent: 4677318 (1987-06-01), Veenstra
patent: 4684830 (1987-08-01), Tsui et al.
patent: 4697097 (1987-09-01), Rusznyak
patent: 4698531 (1987-10-01), Jones

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