Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-12-05
2006-12-05
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185100, C365S185240, C365S185260, C365S185280
Reexamination Certificate
active
07145802
ABSTRACT:
A method for programming a split gate memory cell comprises the following steps. First, a split gate memory cell formed on a semiconductor substrate of a first conductive type, e.g., p-type, is provided. The split gate memory cell has two bitlines of a second conductive type, e.g., n-type, a select gate, a floating gate, a wordline and a dielectric layer deposited between the floating gate and the semiconductor substrate, wherein the select gate and floating gate are transversely disposed between the two bitlines, the wordline is above the select gate and floating gate. Second, a positive voltage is applied to the wordline so as to turn on the floating gate, and a negative voltage is applied to the bitline next to the floating gate, whereby a bias voltage across the tunnel dielectric layer is generated for programming, that is, the so called F-N programming.
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Chang Wen-Lin
Chen Hsin-Chien
Lee I-Long
Liu Yi-Ching
Shone Fuja
Nguyen Viet Q.
Skymedi Corporation
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