Programming a flash memory cell

Details Programming a flash memory cell Programming a flash memory cell

2002-08-29

2004-07-06

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185330, C365S185280, C365S189011, C365S185030

Reexamination Certificate

active

06760257

ABSTRACT:

DESCRIPTION OF THE INVENTION
1. Field of the Invention
The invention relates generally to systems and methods for programming a flash memory cell, and more particularly, to systems and methods for programming a flash memory cell wherein the flash memory cell is capable of storing two bits.
2. Background of the Invention
The use of memory products and systems in the day-to-day lives of most people is continually growing. With the advent and steady growth of computer based systems, wireless telecommunications, and the Internet, memory products and systems must increasingly become smaller, faster, and less expensive. In an effort to lower operating costs and increase value for their customers, providers and programmers of memory products and systems wish to program flash memory cells accurately and efficiently, especially those flash memory cells capable of storing two bits. Providers and programmers of memory products and systems may attract new users and customers to their products and systems or may tend to retain current users and customers by providing methods and systems for accurately and efficiently programming flash memory cells. Thus, providers and programmers of memory products and systems may realize a competitive advantage by providing methods and systems for accurately and efficiently programming flash memory cells capable of storing two bits.
Therefore, the need for systems and methods for programming flash memory cells has become a common need for many providers and programmers of memory products and systems. More specifically, methods and systems for accurately and efficiently programming flash memory cells capable of storing two bits has become critical for many providers and programmers of memory products and systems. This is because in an increasingly competitive environment, meeting and exceeding the expectations of customers or others who receive products or services is essential for flash memory products and systems providers.
One solution to the flash memory cell programming problem for flash memory cells capable of storing two bits is to simply program one bit in the flash memory cell to a particular programming voltage level, for example, a high V
t
state, without regard for the present programming state of the other bit within flash memory cell. Great inefficiencies are created in this procedure because, for example, if programming a second bit to a high V
t
state when a first bit is in a high V
t
state, the V
t
value of the first bit will become higher after the second bit is programmed.
FIG. 5
illustrates the problem with this conventional solution. A graph
505
illustrates the average high V
t
levels of the two bits programmed for a plurality of memory cells in a memory array, the x axis being the number of memory cells cycling in the array and the y axis being the V
t
level. Curve
510
illustrates the average V
t
of a first bit programmed in time in a two-bit memory cell, curve
515
illustrates the average V
t
of a second bit programmed in time in a two-bit memory cell, and curve
520
illustrates the average V
t
of the first bit programmed in time after the second bit is programmed. As can be see from
FIG. 5
, programming the second bit to a high V
t
level causes an increase of the high V
t
of the first bit previously programmed to the same high V
t
level.
The disadvantages of the conventional method are illustrated in FIG.
6
A and FIG.
6
B.
FIG. 6A
illustrates a probabilistic distribution
605
of the V
t
of a plurality of first bits programmed in time in a given memory array.
FIG. 6B
illustrates the probabilistic distribution
610
of the V
t
of a plurality of second bits programmed in time in time in a given memory array and the probabilistic distribution
615
of the V
t
of the plurality of the first bits programmed in time after the second bit is programmed. As shown by
FIG. 6B
, one disadvantage is that the probabilistic distribution of the first bits will become wider and higher after programming the second bits. And as a second disadvantage, because the V
t
of the first bit becomes higher, more area must be erased in order to balance the second bit effect. Therefore, it may be over-erased due to the highest V
t
in one memory cell. Accordingly, efficiently providing systems and methods for programming flash memory cells wherein the flash memory cells are capable of storing two bits remains an elusive goal.
Thus, there remains a need for systems and methods for programming flash memory cells. In addition, there remains a need for systems and methods for programming flash memory cells wherein the flash memory cells are capable of storing two bits each.
SUMMARY OF THE INVENTION
Consistent with the present invention, methods and systems for programming a flash memory cell are provided that avoid problems associated with prior methods and systems for programming a flash memory cell as discussed herein above.
In one aspect, a method for programming a flash memory cell comprises receiving a first V
t
corresponding to a first bit stored in the flash memory cell, receiving a second V
t
corresponding to a second bit stored in the flash memory cell, and programming one of the first bit and the second bit of the flash memory cell with a first programming voltage if the first V
t
and the second V
t
both correspond to a low V
t
state prior to programming the flash memory cell wherein the first programming voltage is &Dgr;V lower than a second programming voltage that is used to program one of the first bit and the second bit of the flash memory cell if either of the first V
t
and the second V
t
correspond to a high V
t
state prior to programming the flash memory cell.
In another aspect, a system for programming a flash memory cell comprises a component for receiving a first V
t
corresponding to a first bit stored in the flash memory cell, a component for receiving a second V
t
corresponding to a second bit stored in the flash memory cell, and a component for programming one of the first bit and the second bit of the flash memory cell with a first programming voltage if the first V
t
and the second V
t
both correspond to a low V
t
state prior to programming the flash memory cell wherein the first programming voltage is &Dgr;V lower than a second programming voltage that is used to program one of the first bit and the second bit of the flash memory cell if either of the first V
t
and the second V
t
correspond to a high V
t
state prior to programming the flash memory cell.
In yet another aspect, a computer-readable medium on which is stored a set of instructions for programming a flash memory cell, which when executed perform stages comprising receiving a first V
t
corresponding to a first bit stored in the flash memory cell, receiving a second V
t
corresponding to a second bit stored in the flash memory cell, and programming one of the first bit and the second bit of the flash memory cell with a first programming voltage if the first V
t
and the second V
t
both correspond to a low V
t
state prior to programming the flash memory cell wherein the first programming voltage is &Dgr;V lower than a second programming voltage that is used to program one of the first bit and the second bit of the flash memory cell if either of the first V
t
and the second V
t
correspond to a high V
t
state prior to programming the flash memory cell.
Both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5953255 (1999-09-01), Lee
patent: 6226200 (2001-05-01), Eguchi et al.
patent: 6307776 (2001-10-01), So et al.
patent: 6643181 (2003-11-01), Sofer et al.
patent: 2002/0021149 (2002-02-01), Park et al.
patent: 2002/0080649 (2002-06-01), Yamada et al.
patent: 2003/0076710 (2003-04-01), Sofer et al.
patent: 2003/0144053 (2003-07-01), Michaelson
patent: 411317087 (1999-11-01), None

Affiliated with

Also associated with

Rating

Programming a flash memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programming a flash memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming a flash memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3256932