Programmed logic array with external signals introduced between

Details Programmed logic array with external signals introduced between Programmed logic array with external signals introduced between

1983-06-20

1984-12-11

Zache, Raulfe B.

Boots, shoes, and leggings

364716, 307465, 34082583, G06F 922

Patent

active

044882300

ABSTRACT:
A combinational logic device, such as an AND gate, is connected to control the flow of information along a wordline from the AND plane to the OR plane of a PLA (programmed logic array). To each such combinational logic device is applied an input signal from a source external to the PLA, so that the PLA's output can respond relatively quickly to this input signal--that is, the PLA is capable of relatively quick decision making.

REFERENCES:
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patent: 3974366 (1976-08-01), Hebenstreit
patent: 4032894 (1977-06-01), Williams
patent: 4034356 (1977-07-01), Howley et al.
patent: 4124899 (1978-11-01), Birkner et al.
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patent: 4409499 (1983-10-01), Zapisek et al.
patent: 4415818 (1983-11-01), Ogawa et al.
patent: 4429238 (1984-01-01), Harrison
J. C. Logue et al., "PLA Test Enhancement", IBM Tech. Discl. Bull., vol. 23, No. 3, Aug. 1980, pp. 1116-1117.
D. A. Kluga, "Clocked PLA w/Dummy Circuit Forming Clock Pulse for Inter-Array Driver w/Worst-Case Delay", IBM T.D.B., vol. 24, No. 6, Nov. 1981.
Howley et al., "Programmable Logic Array Decoding Technique", IBM Tech. Discl. Bull., vol. 17, No. 10, Mar. 1975, p. 2988.
E. Hebenstreit et al., "High-Speed Programmable Logic Arrays in ESFI SOS Technology", IEEE Journal of Solid-State Circuits, vol. SC-11, Jun. 1976, pp. 370-374.
R. H. Krambeck et al., "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid-State Circuits, vol. SC-17, Jun. 1982, pp. 614-619.
C. Mead et al., Introduction to VLSI Systems, 1980, pp. 75-84.

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