Programmed logic array with auxiliary pull-up means to increase

Details Programmed logic array with auxiliary pull-up means to increase Programmed logic array with auxiliary pull-up means to increase

1983-04-11

1986-03-18

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

34082591, 307465, 307468, 365203, H03K 19173, G06F 738

Patent

active

045771901

ABSTRACT:
In a programmed logic array (PLA) having a crosspoint AND plane and a crosspoint OR plane, each of these planes has input lines and output lines intersecting at crosspoints across each of which a transistor driver is connected or not, depending upon the details of the desired logic transformation function of the plane. Each output line is connected to a separate clocked pull-up (or precharge) transistor for precharging that line, and the source terminal of each driver is connected to a clocked pull-down transistor for logic evaluation or computation. In order to reduce the time needed for precharging, the source terminal of every driver is connected to another clocked pull-up transistor.

REFERENCES:
patent: 3974366 (1976-08-01), Hebenstreit
patent: 4037089 (1977-07-01), Horninger
IEEE Journal of Solid State Circuits, vol. SC-11, "High-Speed Programmable Logic Arrays in ESFI SOS Technology," 1976, pp. 370-374, by E. Hebenstreit et al.

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