Multiplex communications – Wide area network – Packet switching
Patent
1995-07-18
1999-02-16
Dung, Dinh C.
Multiplex communications
Wide area network
Packet switching
39520066, 395868, 370463, G06F 1300, G06F 1332
Patent
active
058729208
ABSTRACT:
In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
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Connery Glenn W.
Hausman Richard
Reid Richard S.
Rivers James P.
Sherer Paul William
3Com Corporation
Dung Dinh C.
LandOfFree
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