Programmed I/O ethernet adapter with early interrupt and DMA con

Details Programmed I/O ethernet adapter with early interrupt and DMA con Programmed I/O ethernet adapter with early interrupt and DMA con

1998-02-23

2000-08-29

Dinh, Dung C.

Electrical computers and digital processing systems: multicomput

Network-to-computer interfacing

710 25, 710 57, G06F 1300, G06F 1332

Patent

active

061122521

ABSTRACT:
In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

REFERENCES:
patent: 5210749 (1993-05-01), Firoozmand
Advanced Micro Devices, "The SUPERNET 2 Family for FDDI--1991/1992 World Network Data Book".

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