Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-11-15
2003-11-18
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S540000, C330S086000, C330S287000
Reexamination Certificate
active
06650173
ABSTRACT:
TECHNICAL FIELD
The invention relates to a programmable voltage generator, particularly for programming multilevel non-volatile memory cells.
BACKGROUND OF THE INVENTION
As is known, a multilevel memory cell, of the flash type for example, may be programmed so as to exhibit one of N threshold voltages (or more precisely one of N distributions of the threshold voltage) and is therefore capable of storing a number M=log
2
N.
The requirements for programming a multilevel memory are much more stringent compared with two level memories: in particular, to obtain an adequate accuracy of the programmed levels it is necessary for the cells to have threshold voltages distributed in intervals which are sufficiently narrow and spaced in a reduced time.
For example, according to a known solution, a stepped voltage which increases linearly with a pre-determined increment is supplied to the selected word line connected to the gate terminal of the cell to be programmed.
This increment must be defined with the utmost accuracy in view of the fact that there is a linear relationship between the increase in the threshold voltage &Dgr;V
T
of the cell to be programmed and the increment of the gate voltage &Dgr;V
GP
applied, if the drain voltage of the cell to be programmed is kept constant.
To program four level cells for example it is possible to use a stepped voltage which increases from a minimum value equal to 1.5 V up to a maximum value equal to 9 V, with constant increment equal to approx. 300 mV.
According to a known solution, a voltage generator of the type shown in
FIG. 1
is used to obtain the above-mentioned stepped voltage.
In detail,
FIG. 1
shows a voltage generator
2
included in a memory device
1
of multilevel type and having an input terminal
2
a
connected to a reference generator
3
, of the band-gap type for example, supplying a reference voltage V
BG
, and an output terminal
2
b
at which an output voltage V
0
is present.
The voltage generator
2
comprises a differential amplifier
4
, an operational amplifier for example, having a power supply terminal
4
a
connected to a power supply line
5
set at a supply voltage V
PP
, a non inverting input
4
b
connected to the reference generator
3
and an inverting input
4
c
connected to a feedback node
6
. The operational amplifier
4
further has an output terminal coincident with the output terminal
2
b
of the voltage generator
2
.
A voltage divider
9
is connected between the output terminal
2
b
of the voltage generator
2
and a ground terminal GND and comprises a feedback resistor
8
, having a constant resistance R
1
, and a programmable resistor
10
, having a variable resistance R
2
, as illustrated in detail below. The feedback resistor
8
is connected between the ground terminal GND and the feedback node
6
, the programmable resistor
10
is connected between the feedback node
6
and the output terminal
2
b.
The voltage generator
2
operates as follows.
During each programming phase of the memory device
1
, because of the feedback supplied at the inverting input
4
c
of the operational amplifier
4
, the output voltage V
0
depends on the reference voltage V
BG
and on the resistances R
1
and R
2
according to the expression:
V
0
=
V
BG
(
1
+
R
2
R
1
)
(
1
)
By increasing the resistance of the programmable resistor
10
by a value R
2
*, a corresponding increment in the output voltage V
0
is obtained, which is equal to:
Δ
V
0
=
V
BG
(
R
2
*
R
1
)
(
2
)
The voltage divider
9
is generally produced as shown in
FIG. 2
, in which the programmable resistor
10
comprises a fixed resistor
21
.
0
, of resistance R
0
, and a plurality of additional resistors
21
.
1
,
21
.
2
, . . . ,
21
.n, of resistance R.
1
, R.
2
, . . . , R.n and disposed in series with each other between the output terminal
2
b
and the fixed resistor
21
.
0
. For example, the additional resistors
21
.
1
,
21
.
2
, . . . ,
21
.n may be constituted by a string of resistors having a resistance which increases with the powers of two, i.e., for example, if the additional resistor
21
.
1
has a resistance Rx, the successive additional resistors
21
.
2
,
21
.
3
, . . . ,
21
.n have a resistance of 2Rx, 4Rx, . . . , 2
N−1
Rx. A selection switch
26
.
1
,
26
.
2
, . . . ,
26
.n, produced as a CMOS switch for example, controlled by a respective command signal, is connected in parallel with each additional resistor
21
.
1
,
21
.
2
, . . . ,
21
.n.
The number of selection switches
26
.
1
,
26
.
2
, . . . ,
26
.n which must be opened or closed from time to time depends on the value of R
2
it is desired to program, given that the additional resistors
21
.
1
,
21
.
2
, . . . ,
21
.n which do not contribute to the desired resistance value R
2
are each short circuited by a respective selection switch
26
.
1
,
26
.
2
, . . . ,
26
.n.
This known solution does, however, have a number of disadvantages. Primarily the output voltage V
0
is not linear.
In fact, although the selection switches
26
.
1
,
26
.
2
, . . . ,
26
.n individually have a small resistance which is negligible compared to the resistances of the respective additional resistors
21
.
1
,
21
.
2
, . . . ,
21
.n, they introduce a resistance error which causes a mismatching between the resistance R
1
of the feedback resistor
8
and the resistance R
2
of the programmable resistor
10
. Furthermore, the resistance error is not constant but depends on the number of closed selection switches
26
.
1
,
26
.
2
, . . . ,
26
.n, and cannot therefore easily be compensated. If a large number of selection switches
26
.
1
,
26
.
2
, . . . ,
26
.n is closed the resistance error becomes substantial and comprises a substantial error on the output voltage V
0
.
In this connection reference is made to
FIG. 3
which shows, as a function of the number n of programming steps, the plot of the ideal voltage V
0ID
(unbroken line) and of the actual voltage V
0RE
obtained at the output of the voltage generator
2
(dashed line).
The non linearity of the output voltage V
0
may be quantified by means of the non linearity error &egr;
d
defined by the expression:
ϵ
d
=
&LeftBracketingBar;
V
0
ID
(
i
)
-
V
0
RE
(
i
)
&RightBracketingBar;
Δ
V
GP
where V
0ID
(i) and V
0RE
(i) are the ideal and actual values of the output voltage V
0
at the i'th programming step and &Dgr;V
GP
is the programmed increment of the gate voltage of the cell to be programmed and coincides with &Dgr;V
0
.
In practice, the use of the voltage divider
9
of
FIG. 2
results in a differential error &egr;
d
on the order of approx. ±15%.
A further disadvantage of this known solution is due to the presence of a voltage spike at the feedback node
6
following the switching of the selection switches
26
.
1
,
26
.
2
, . . . ,
26
.n. This voltage spike, which slows down the rise of the output voltage V
0
, is due to the injection of charge at the feedback node
6
and its amplitude depends on the number of selection switches which switch contemporaneously with the change in the value to be programmed. Furthermore the injection of charge is particularly high when the selection switches are of large dimensions, as may be demanded by linearity requirements.
On the other hand, to ensure that the output voltage V
0
assumes a correct value in a reduced time, as required for programming multilevel cells, it is necessary to reduce the voltage spike at the feedback node
6
to a minimum.
SUMMARY OF THE INVENTION
A voltage generator is provided which drastically reduces the disadvantages described.
The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with
Khouri Osama
Micheloni Rino
Sacco Andrea
Torelli Guido
Bennett, II Harold N.
Cunningham Terry D.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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