Programmable viterbi signal processor

Details Programmable viterbi signal processor Programmable viterbi signal processor

1990-11-30

1993-06-15

Baker, Stephen M.

Excavating

341 78, 341 94, 341107, H03M 1300, H03M 1312, H03M 728

Patent

active

052205703

ABSTRACT:
A signal processor which is specially adapted for decoding sequential codes, including trellis codes, convolutional codes and detecting signals in partial response channels. The processor has three units, a branch metric generator unit, an add-compare-select unit and a survivor-trace and decoding unit, each of which is independently programmable. A central control unit synchronizes operations between the units at the received symbol rate. Between synchronizations, each of the units operate concurrently and independently of the others.

REFERENCES:
Clark, G. et al., Error-Correction Coding for Digital Communications, Plenum Press, New York, 1981, pp. 254-264.
Gulak, P. et al., "VLSI Structures for Viterbi Receivers: Part I-General Theory and Applications", IEEE Journal on Selected Areas in Communications, vol. SAC-4, No. 1, Jan. 1986, pp. 142-154.
Frenet, N. et al., "Implementation of a Viterbi Processor for a Digital Communications System with a Time-Dispersive Channel", IEEE Journal on Selected Areas in Communications, vol. SAC-4, No. 1, Jan. 1986, pp. 160-167.
Fettweis, G. et al., "A 100 MBit/S Viterbi Decoder Chip: Novel Architecture and Its Realization", 1990 Int'l Conference on Communications, Apr. 1990, Paper No. 307.4.

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