Programmable variable length decoder circuit and method

Details Programmable variable length decoder circuit and method Programmable variable length decoder circuit and method

2002-09-13

2004-01-06

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

C341S061000, C341S063000, C341S065000

Reexamination Certificate

active

06674376

ABSTRACT:

BACKGROUND
This invention relates to digital content, and more particularly to a decoder for fixed- and variable-length codewords (VLC). Digital content such as video can be transmitted as a series of bit streams encoded according to one of various encoding standards. For example, some standards fall under the auspices of the Moving Pictures Expert Group (MPEG), a joint committee of the International Standards Organization (ISO) whose purpose is to develop standards for the compression, encoding, etc. of digital media. MPEG standards include MPEG-1, MPEG-2, and MPEG-4. Other digital content encoding standards exist, including standards for digital images by the Joint Photographic Experts Group (JPEG), and for High Definition Television (HDTV). A digital content stream that is encoded for transmission conventionally requires a decoder to translate the encoded bit streams into a format that can be output and rendered.
An encoded bit stream generally consists of a sequence of variable-length and fixed-length codewords. Each codeword represents a discrete cosine transfer (DCT) coefficient, motion vector element, macroblock type, coded block pattern, image parameter, and so on. The DCT coefficients need to be generated at certain high speeds. For example, for decoding HDTV streams, DCT coefficients need to be generated at approximately 100 MHz. To achieve this speed, a decoder needs to be self-controlled. In other words, the decoder must be able to decode the DCT coefficients of several 8-pixel×8-pixel blocks without the intervention of a host processor.
Conventional decoders use complex table-lookup memory devices for storing a code length and associated value for each codeword. The table-hookup memory devices are typically implemented with content addressable memory (CAM), programmable logic devices (PLDs), or a combination of a PLD and several random access memories (RAMs). In addition, decoders which use these types of memory devices require a controller, which contains an additional memory device for storing the protocol or instructions according to which the controller operates.
Several problems with conventional decoders includes high costs, limited programmability, and complicated testing procedures. CAM or PLD is generally much more expensive than RAM. Moreover, existing decoders need multiple memory devices, which complicates testing procedures and also limits the decoder's programmability because the capacity for each memory device is usually fixed.
SUMMARY OF THE INVENTION
The above problems are solved by a decoder which uses a single RAM device for storing all of the look-up tables as well as decoder protocols. Because there is only a single RAM device, the decoder is simple and highly flexible. In addition, the decoder does not require costly CAM or PLDs. To realize the full function of a decoder with a single RAM, an embodiment of the decoder includes a program counter whose value is controllable by the RAM contents as well as binary values in the input stream. The decoder also includes a condition register for controlling the value of the program counter. The decoder is applicable to different coding standards including MPEG-1, MPEG-2, MPEG-4, and JPEG, and has a sufficient performance for decoding HDTV video streams.
In one embodiment, an apparatus includes a memory, a first barrel shifter, a second barrel shifter, a microprogram counter, a data converter, and a data storage. The memory stores microinstructions that control the apparatus. The first barrel shifter extracts a first bit field from the bit stream, a position of the first bit field being specified by the microinstructions. The second barrel shifter extracts a second bit field from the bit stream, a position of the second bit field being specified by the microinstructions. The microprogram counter keeps an address of a currently-executing microinstruction of the microinstructions, a next state of the microprogram counter being determined by the microinstructions and the first bit field. The data converter modifies a value of the second bit field according to the microinstructions. The data storage stores either data in the microinstructions or an output of the data converter as decoded data values.
In another embodiment, a method includes accessing a sequence of microinstructions that are stored in a microprogram memory; extracting a first bit field from the bit stream, a position of the first bit field being specified by the microinstructions; and extracting a second bit field from the bit stream, a position of the second bit field being specified by the microinstructions. The method further includes keeping an address of a currently-executing microinstruction of the microinstructions, a next state of the microprogram counter being determined by the microinstructions and the first bit field. The method further includes modifying a value of the second bit field according to the microinstructions. The method further includes storing either data in the microinstructions or an output of the data converter as decoded data values.
Numerous additional embodiments are also possible.


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