Programmable unit having plural levels of subinstruction sets wh

Details Programmable unit having plural levels of subinstruction sets wh Programmable unit having plural levels of subinstruction sets wh

1988-10-07

1990-12-04

Eng, David Y.

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3642431, 3642437, 3642446, 3642455, 3642459, 3642461, 3642581, 3642627, 3642628, G06F 922, G06F 930, G06F 1316

Patent

active

049758373

ABSTRACT:
A processor has two levels of subinstructions, each stored in its own memory with the lower level memory containing only a limited set of such lower level instructions with the rest of the lower level instructions that are desired to be used being supplied by the code stream from the upper level memory.

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