Multiplex communications – Channel assignment techniques – Using time slots
Reexamination Certificate
2006-05-02
2006-05-02
Marcelo, Melvin (Department: 2662)
Multiplex communications
Channel assignment techniques
Using time slots
Reexamination Certificate
active
07039064
ABSTRACT:
An apparatus generally comprising a plurality of writeable registers, a control circuit, and a transmitter circuit. The writeable registers may be configured to store (i) a first burst value and (ii) a first gap value. The control circuit may be configured to generate an idle signal (i) in a transmit state for a first duration determined by the first burst value and (ii) in an idle state for a second duration determined by the first gap value in response to a first command signal. The transmitter circuit may be configured to (i) enable transmitting while the idle signal is in the transmit state and (ii) disable transmitting while the idle signal is in the idle state.
REFERENCES:
patent: 2002/0071511 (2002-06-01), Jo et al.
patent: 2002/0110142 (2002-08-01), Ophir et al.
patent: 2002/0167930 (2002-11-01), Pearl
“Serial ATA: High Speed Serialized AT Attachment”, Revision 1.0, Aug. 29, 2001, pp. 1-307.
Paulson Christopher D.
Schauer Steven A.
Christopher P. Maiorana P.C.
LSI Logic Corporation
Marcelo Melvin
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