Programmable time delay circuit for digital logic circuits

Details Programmable time delay circuit for digital logic circuits Programmable time delay circuit for digital logic circuits

1990-06-04

1991-11-05

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307608, 307597, 307494, 328 55, 330280, H03K 5159, G06G 712, H03G 310

Patent

active

050633112

ABSTRACT:
An ECL logic circuit having differential inputs and differential outputs and programmable propagation delay time is provided. The differential inputs are coupled to a first differential amplifier as is done on a conventional differential ECL circuit. A second feedback differential amplifier is coupled to the collectors of the first differential amplifier. Current in the first differential amplifier is normally constant, whereas current in the feedback differential amplifier can be programmably adjusted. By adjusting the current in the feedback differential amplifier the feedback differential amplifier loads the logic circuit forcing a voltage swing which is up to double that normally provided by the first differential amplifier, therefore increasing the time required for either output to change from a logic LOW to a logic HIGH. This delay results in a variable propagation delay which is controlled by adjusting current flow in the feedback differential amplifier.

REFERENCES:
patent: 4152667 (1979-05-01), Visser
patent: 4745310 (1988-05-01), Swapp
patent: 4795923 (1989-01-01), Dobos
patent: 4797586 (1989-01-01), Traa
patent: 4839609 (1989-06-01), Hara et al.

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