Programmable state machine

Details Programmable state machine Programmable state machine

1998-12-10

2001-12-04

Grant, William (Department: 2121)

Data processing: generic control systems or specific application

Generic control system, apparatus or process

Plural processors

C700S001000, C711S203000, C711S220000

Reexamination Certificate

active

06327508

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to hardware state machines for microcontrollers, and more particularly to a programmable state machine.
2. Description of the Related Art
Microcontrollers
As technology advances, computer system components are providing specific services which previously were offered by a microprocessor or the computer system as a whole. A centerpiece of this advancing technology is known as a microcontroller, or embedded controller, which in effect is a microprocessor as used in a personal computer, but with a great deal of additional functionality combined onto the same monolithic semiconductor substrate (i.e., chip). In a typical personal computer, the microprocessor performs the basic computing functions, but other integrated circuits perform functions such as communicating over a network, controlling the computer memory, and providing input/output with the user.
In a typical microcontroller, many of these functions are embedded within the integrated circuit chip itself. A typical microcontroller, such as the Am186EM or Am186ES by Advanced Micro Devices, Inc., of Sunnyvale, Calif., not only includes a core microprocessor, but further includes a memory controller, a direct memory access (DMA) controller, an interrupt controller, and both asynchronous and synchronous serial interfaces. In computer systems, these devices are typically implemented as separate integrated circuits, requiring a larger area and increasing the size of the product. By embedding these functions within a single chip, size is dramatically reduced, often important in consumer products.
From a consumer products designer's viewpoint, often the particular combination of added features make a particular microcontroller attractive for a given application. Many microcontrollers are available that use the standard 80×86 microprocessor instructions, allowing for software to be easily developed for such microcontrollers. Because of the similar execution unit instruction sets, the added features often become principal differentiating criteria between particular microcontrollers.
In implementing microcontrollers in embedded systems, another common requirement or desirable feature is the reduction of the bandwidth needed by any particular portion of the microcontroller in negotiating with other portions. For example, the core of a microcontroller is the execution unit, which is essentially a microprocessor core. An execution unit should be free to perform the programmed task to which it is dedicated, rather than spending time waiting on other units within the microcontroller.
State Machines
For many system control applications, sequential logic designers are utilizing state machines rather than complex microprocessors to provide speed and sufficient functionality without undue complexity. One advantage of transferring certain functions from a microprocessor to a state machine is freeing the microprocessor to perform other functions. Examples of functions which have been efficiently translated into state machines include vector control for a Fast Fourier Transform (FFT) algorithm, addressing by a controller, encoding and decoding, encryption and decryption, arbitration, event monitoring, and simple control functions.
A state machine is essentially a digital device that traverses through a predetermined sequence of states in an orderly fashion. A simple state machine includes two essential elements: combinatorial logic and memory. The memory is used to store the state of the machine. The combinatorial logic may be viewed as two distinct functional blocks: the next state decoder and the output decoder. The next state decoder determines the next state of the state machine while the output decoder generates the actual outputs. A state machine traverses through a sequence of states, where the next state is determined by the next state decoder, depending upon the current state and input conditions. A state machine also provides sequences of output signals based upon state transitions. The outputs are generated by the output decoder based upon the current state and input conditions. There are two widely known types of state machines: Mealy and Moore. Moore state machine outputs are a function of the current state only. In Mealy-type state machines, the outputs are functions of both the current state and the input conditions.
So far as is known, prior art programmable state machines have required state machine functions to be hardwired in silicon.
SUMMARY OF THE INVENTION
Briefly, a system according to the present invention provides a programmable state machine. The programmable state machine may include transition/output logic for providing first signals corresponding to next state and output information, a plurality of state registers for receiving the first signals corresponding to next state and output information and providing second signals corresponding to current state information to the transition/output logic, and a plurality of mask registers for selectively providing third signals corresponding to masking information to the transition/output logic. The programmable state machine may further include a comparator mask coupled between a portion of the plurality of mask registers and a portion of the transition/output logic. The plurality of mask registers may include a plurality of input mask registers for selectively enabling and disabling input values to the transition/output logic and a plurality of transition mask registers for selectively enabling and disabling transition values for the transition/output logic. Further, the plurality of mask registers may include a plurality of level inhibit registers for selectively enabling and disabling logic terms corresponding to a particular level of the transition/output logic.


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