Programmable speed/power arrangement for integrated devices havi

Details Programmable speed/power arrangement for integrated devices havi Programmable speed/power arrangement for integrated devices havi

1989-07-31

1990-11-06

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307465, 3072021, 365227, H03K 1900

Patent

active

049689002

ABSTRACT:
A programmable speed/logic arrangement for integrated devices having logic matrices which permits a user to determine the method by which the a logic matrix of an integrated circuit is switched between a low power standby and a high power operation mode. The arrangement includes a switching circuit for switching the logic matrix between modes, switch operating circuit responsive to at least one of internal and external wake-up pulses for operating the switching circuit, and an internal pulse generator for selectively generating a wake-up pulse internally of the matrix. The logic matrix is provided with a specific addressable location which is responsive to an appropriate address to generate the internal wake-up pulse as well as a dedicated input responsive to an externally generated wake-up pulse. Further, high/low power fuses or E/EE CMOS devices can be employed to programmably connect the logic matrix to different levels of high power sources. The plural power sources may be a plurality of parallel switches for each column.

REFERENCES:
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patent: 4384220 (1983-05-01), Segawa et al.
patent: 4631418 (1986-12-01), Toyomura
patent: 4686386 (1987-08-01), Tadao
patent: 4691123 (1987-09-01), Hashimoto
patent: 4713560 (1987-12-01), Hernden
patent: 4801820 (1989-01-01), Nootbaar
Flaker et al., "Programmed Power Proportioning for PLA's", IBM T.D.B., vol. 18, No. 4, Sep. 1975, pp. 1047-1048.

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