Programmable signal processing device

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G06F 1531

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044545908

ABSTRACT:
The device performs the function ##EQU1## for image processing, where W.sub.i are fixed weights for any specific application. It uses a PROM and accumulator algorithm, in which the memory stores the values ##EQU2## in 2.sup.M words, with addresses formed from one bit of each data word in a given bit position. In operation the most significant bit of each data word is used first to address memory, and in successive clock cycles the other bit positions are used down to the least significant. The memory output words are supplied to the adder-accumulator, and in each clock cycle the adder-accumulator output is shifted left one bit and used as a second input thereof. Then if the data words have N bits designated j=0 to N-1, after N clock cycles the memory output words have each been effectively multiplied by 2.sup.j and accumulated in the sum.

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patent: 4218752 (1980-08-01), Hewes et al.
H. J. DeMan et al., "High Speed NMOS Circuits for ROM-Accumulator and Multiplier Type Digital Filter", IEEE Journal Solid State Circuits, vol. SC-13, (Oct. 1978), p. 565.
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IEEE Proc., vol. 128, Pte., No. 3, May 1981, Speed Optimized Microprocessor Implementation of a Digital Filter, B. S. Tan & G. J. Hawkins, pp. 85-94.

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