Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1997-10-10
2001-10-30
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S276000, C327S525000
Reexamination Certificate
active
06310506
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electronic devices, and more particularly, to a programmable time delay network for use with semiconductor devices requiring signal delays.
BACKGROUND OF THE INVENTION
Semiconductor device technology continues to rapidly advance in the area of devices requiring setup and hold times for input signals. Specifically, dynamic random access memory (DRAM) technology has developed recently to reduce the dissociation of the operation speed between the microprocessor unit of the computer and the DRAM. In a DRAM, a predetermined clock signal is supplied to a clock input terminal. Synchronizing with this predetermined clock signal allows direct contact operation between the DRAM and the microprocessor.
High speed semiconductor parts necessitate relatively tight setup and hold time specifications for DRAMs. Due to the increasing operational speed of DRAMs, a relatively short setup/hold time window exists during which to sample an input signal (e.g., a row or column address strobe signal) in a DRAM. For example, a DRAM for a 125 MHZ microprocessor can have a 2 ns setup time and a 1 ns hold time specification. The inherent time delays in the circuit can cause the rising edge of a clock signal (or latching signal) to miss the setup/hold time window in the input signal, thus failing to enable the DRAM. Building a delay into the path traveled by the input signal can help delay the input signal to allow enough time for the clock signal to travel through the circuit.
Conventional DRAMs do not include any delay mechanism or delay circuit that can be adjusted after fabrication of the device to alter the amount of time the input signal is delayed. Therefore, these conventional DRAMs cannot adjust the setup/hold times to move the setup/hold time window to a point that can be utilized after the device is fabricated. This lack of ability to adjust the delay in the input signal path can result in fabrication of inoperable devices because of the relative difficulty in predicting the location of the input signal setup/hold time window prior to fabricating the device. Furthermore, as the speed of operation increases, the setup/hold time window will become increasing smaller, resulting in a greater number of inoperable devices.
SUMMARY OF THE INVENTION
The present invention provides a programmable setup/hold time delay system and method that substantially eliminates or reduces disadvantages and problems associated with previously developed setup/hold time delay systems and methods.
More specifically, the present invention provides a system for subjecting an input signal going to a DRAM to a programmable delay. The programmable delay network can comprise at least one delay device connected with at least one time delay adjustment mechanism. The time delay adjustment mechanism(s) (for example, a fuse) can connect to the delay device(s) in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.
In one embodiment, the programmable delay network can comprise at least one metal plate capacitor. A portion of the metal plate capacitor can be removed in order to change the amount of delay time the input signal experiences through the delay network.
The present invention provides an important technical advantage with an adjustable time delay network that can be programmed to subject the input signal to varying time delays after fabrication of the device. The present invention allows the setup/hold time window to be adjusted after a DRAM device has been built.
The present invention provides another technical advantage by increasing the yield of devices, including DRAM devices.
The present invention provides yet another technical advantage by providing a solution to the problem of using DRAMS with increasingly smaller setup/hold time windows. The adjustable time delay of the present invention can reduce the difficulty of sampling the input signal at the appropriate time as the setup/hold times decrease in faster generations of DRAM devices.
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Brady W. James
Callahan Timothy P.
Cimino Frank D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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