Programmable sequence controller with an arithmetic operation fu

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06F 1516, G06F 1546

Patent

active

042492483

ABSTRACT:
A programmable sequence controller wherein a logic operation processor controls a program counter so as to successively read out from a sequence memory sequence instructions, which are applied to an input and output selector for selectively designating a plurality of input and output elements as well as to the logic operation rocessor. The logic operation processor is programmed to test the operational states of one or more input elements when receiving test commands and to output an energization or deenergization signal based upon the test result when receiving an output command. An output drive device is provided, which energizes or deenergizes selected one of the output elements in response to the energization or deenergization signal. Each of the sequence instructions includes therein any of an arithmetic operation command and the test and output commands, and when the arithmetic operation command is read out, an interrupt is applied to an arithmetic operation processor, which is thus enabled to execute the arithmetic operation command.

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patent: 3944984 (1976-03-01), Moorley
patent: 4034354 (1977-07-01), Simmons
patent: 4064395 (1977-12-01), Schubeler
patent: 4077060 (1978-02-01), Bodner et al.
patent: 4079455 (1978-03-01), Ozga
patent: 4086658 (1978-04-01), Finlay
patent: 4129901 (1978-12-01), Masuda

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