Programmable semiconductor memory device with combined sense amp

Details Programmable semiconductor memory device with combined sense amp Programmable semiconductor memory device with combined sense amp

1985-07-26

1987-09-15

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

365210, 365205, G11C 1140

Patent

active

046944273

ABSTRACT:
A semiconductor memory device provided with first and second bit lines, each of which is connected to a memory cell comprising a nonvolatile transistor and a dummy cell comprising a nonvolatile transistor. The first and second bit lines are respectively connected to high voltage generators which are applied at the time of data programming. At the time of data reading, data-detecting and storing means comprising a flip-flop circuit detects data, while amplifying a potential difference between the first and second bit lines. At the time of data writing, the data detecting and storing means temporarily stores data in accordance with the contents of externally supplied writing data. A first switching transistor is provided between the first data input-output node of the data-detecting and storing means and the first bit line. The second switching transistor is connected between the second data input-output node of the data-detecting and storing means and second bit line. The paired switching transistors are controlled in accordance with the operation mode of the memory device.

REFERENCES:
patent: 4031524 (1977-06-01), Heeren
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4459684 (1984-07-01), Chapman
Chao et al, "CMOS Sense Restore Circuits for One Device FET Dynamic RAM", IBM Tech. Disc. Bull., vol. 25, No. 10, Mar. 1983, pp. 5088-5091.
"Nikkei Electronics Journal", pp. 171-184, Jan. 16, 1984.

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