Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-09-11
2000-08-22
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518517, 36518519, 36518529, G11C 1606
Patent
active
061082384
ABSTRACT:
The nonvolatile semiconductor memory device comprises a memory cell array in which memory cell units having one or more reprogrammable nonvolatile memory cells are arranged in an array, a word line commonly connected to a same row of the one or more memory cells of the memory cell array, a data line commonly connected to a same column of the memory cell units of the memory cell array, sequence control section for controlling a sequence operation which reprograms data of the selected memory cell by a first operation for applying the voltage to reprogram data of the selected memory cell, and a second operation for verifying reprogrammed state of data to memory cell to which the voltage is applied, and voltage application section for applying to the first voltage higher than a power supply voltage to the word line corresponding to the memory cell to be data reprogrammed in the first period which is corresponds to at least partial period during a period of the first operation, in which in a second period corresponding to at least a part in periods which excludes the first period during the sequence operation, a setting voltage of the level of the first voltage is set to the voltage different from a setting voltage of a voltage level in the first period.
REFERENCES:
patent: 5768190 (1998-06-01), Tanaka et al.
patent: 5768191 (1998-06-01), Choi et al.
patent: 5801989 (1998-09-01), Lee et al.
Akita Kazushi
Nakamura Hiroshi
Sato Takeaki
Ho Hoai V.
Kabushiki Kaisha Toshiba
Nelms David
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