Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
1999-11-15
2002-10-29
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C430S130000
Reexamination Certificate
active
06472253
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the programming of devices of semiconductor chips, and more particularly, to the forming of programmable devices and the selective programming of such devices.
2. Description of the Related Art
Recently, there have been many advances in the fabrication of semiconductor devices, which have led to the continued development of smaller and smaller semiconductor chips. Due to these advances, miniature chips are finding a number of new applications. Such applications include, for example, automated teller machine (ATM) cards, identification cards, security access cards, set-top boxes, cellular phones, and the like. Integrated chips bring these type of applications substantially more intelligence than was previously possible with magnetic strips and other static data storage. Applications such as these, however, require chips that can be programmed with specific passwords, programs, or codes in order to store information that is either unique to the user, or specific to the chip.
Traditionally, the manufacturer of the chip may be required to program codes or set wiring after the chip is packaged using laser fuse technology or before packaging using antifuse technology. As is well known to those skilled in the art, laser fuse technology requires that a fuse structure (that is in the form of a metal line) be blown apart to prevent future electrical conduction. Although fuse technology is capable of providing programmability, a polysilicon-type fuse (which is most common), necessarily prevents a certain amount of chip area from being used for active circuitry. Typically, fuses that utilize a laser for obliteration need to be placed sufficiently away from active circuitry because of the potential for collateral damage to other circuit elements from the laser pulse or by subsequent damage associated with damage to the passivation and inter-metal oxides (IMO) layers at the fuse locations. Additionally, fuses that require laser obliteration need to adhere to specific spacing requirements to ensure that there is no thermal coupling between devices or inadvertent programming of other fuses.
Antifuse technology, on the other hand, defines a link between two metal layers by forming links through an amorphous silicon layer. As can be appreciated, implementing antifuse structures into a custom chip design requires a number of special fabrication operations to make the antifuse structures. In addition, some antifuse structures require even more chip area than fuses. More importantly, the programming of antifuses requires that enough current is passed between two metal layers to create a silicided link between the selected metal lines. Although antifuse technology can be used, it is also known to be somewhat unreliable. That is, fuses that appear programmed at one point in the chip's operational life may become de-programmed unexpectedly. Most importantly, the fabrication of a limited number of antifuse devices onto an application specific integrated circuit (ASIC) may drive the cost of fabrication too high to make the chip practical for certain consumer applications.
FIG. 1A
describes yet another technique for forming a conductive link in accordance with the prior art.
FIG. 1A
illustrates heating a metallization line
20
to form cracks
22
a
-
22
d
in a semiconductor device
11
. The cracks
22
a
-
22
d
will ultimately serve to connect the metallization line
20
with a metallization line
18
.
FIG. 1A
shows the metallization line
20
being subjected to a high energy heat source, such as laser energy
32
from a laser
30
. As the metallization line
20
begins to melt, it expands causing the cracks
22
to form throughout the semiconductor device
11
as shown. As the cracks
22
propagate, crack formation lines
22
a
,
22
b
,
22
c
and
22
d
form. Eventually, the crack line
22
c
propagates through oxide layer
14
to the metallization line
18
. As the metallization line
20
melts, it seeps into crack line
22
c
. The metallization line
20
continues to seep through the path defined by the crack
22
c
until it comes into contact with the metallization line
18
. Thus, a conductive link is formed through the crack
22
c
whereby the metallization line
20
is in conductive contact with the metallization line
18
.
The technique used in the prior art as shown in
FIG. 1A
has many drawbacks. As the metallization line
20
expands, large stresses in the metal/dielectric around the metallization line build up and cracking around the corners usually results. Furthermore, the cracks themselves are difficult to control, thereby making this technique unreliable. Also, the mere existence of the cracks pose a reliability problem. These disadvantages render the technique undesirable.
In view of the foregoing, there is a need for a method of making a programmable structure, which can be cost effectively fabricated and is capable of being compactly designed into any type of integrated circuit structure. There is also a need for programmable structures that do not occupy chip area that needs to be used for active devices and do not cause damage to neighboring devices when programmed. Additionally, the method for making the programmable structure must not create cracks and unduly stress the semiconductor device.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a programmable structure that can be laser programmed to form a hard-wired link, and methods for making the programmable structure. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a programmable device is disclosed. The programmable device includes a link metallization line and a via hole that is defined in an oxide layer that is above the link metallization line. The via hole defines a path to the link metallization line. A programming metallization line is patterned over the oxide layer and the programming metallization line has an overlap portion which lies over the via hole. The overlap portion is configured to melt into the via hole to define a programming link between the link metallization line and the programing metallization line.
In another embodiment, a method for making a programmable device is disclosed. A link metallization line is formed with an oxide layer deposited over the link metallization line. Next, a conductive via is defined within the oxide layer which is in communication with the link metallization line. A programing metallization line is then patterned over the oxide layer such that an overlap portion of the programming metallization line lies over the conductive via. The conductive material is subsequently removed from the conductive via to define a via hole that forms a path between the programming metallization line and the link metallization line. Once the conductive material is removed, part of the overlap portion of the programming metallization line is melted into the via hole to define a programming link. The programming link connects the link metallization line to the programming metallization line.
In yet a further embodiment, another method for making a programmable device is disclosed. A link metallization line is formed with an oxide layer over the link metallization line. A conductive via is then formed in the oxide layer that is in communication with the link metallization line. After the conductive via is formed, a programmable metallization line is patterned over the oxide layer to define an overlap portion of the programmable metallization line. The overlap portion is defined to at least partially overlap the conductive via. Next, a conductive material within the conductive via is removed to define a via hole which creates a path between the programming metallization lines and the link metallization line. A second oxide layer is then formed over the pro
Brewster William M.
Dang Trung
VLSI Technology Inc.
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