Programmable scan chain testing structure and method

Details Programmable scan chain testing structure and method Programmable scan chain testing structure and method

1996-04-30

1997-10-07

Voeltz, Emanuel T.

Excavating

39518306, 364488, 364489, 364490, 364491, G01R 31311

Patent

active

056755899

ABSTRACT:
A circuit and method for testing Field Programmable Gate Arrays (FPGAs) comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contains an edge cell comprising a multi-input multiplexer, one of the multiplexer inputs being dedicated to receiving a signal from an adjacent cell, other of the inputs being connected to gate array input pads. A programmable control signal on the multiplexer enables the column to either receive test data from one of the gate array input pads or to connect as part of a scan chain by receiving a wrapping signal from the output logic cell of an adjacent column.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4706216 (1987-11-01), Carter
patent: 4750155 (1988-06-01), Hsieh
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4821233 (1989-04-01), Hsieh
patent: 4870302 (1989-09-01), Freeman
patent: 4931671 (1990-06-01), Agrawal
patent: 5148390 (1992-09-01), Hsieh
patent: 5198705 (1993-03-01), Galbraith et al.
patent: 5221865 (1993-06-01), Phillips et al.
patent: 5231588 (1993-07-01), Agrawal et al.
patent: 5237219 (1993-08-01), Cliff
patent: 5243238 (1993-09-01), Kean
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5280202 (1994-01-01), Chan et al.
patent: 5341044 (1994-08-01), Ahanin
patent: 5347519 (1994-09-01), Cooke et al.
patent: 5376844 (1994-12-01), Pedersen et al.
patent: 5384499 (1995-01-01), Pedersen et al.
patent: 5394031 (1995-02-01), Britton et al.
patent: 5394034 (1995-02-01), Becker et al.
patent: 5430687 (1995-07-01), Hung et al.
patent: 5453706 (1995-09-01), Yee
patent: 5495487 (1996-02-01), Whetsel, Jr.
Xilinx, Inc., The Programmable Logic Data Book, 1993, pp. 1-1 through 1-7; 2-1 through 2-42; 2-97 through 2-130; and 2-177 through 2-204, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx Programmable Gate Array Data Book, 1989, pp. 6-30 through 6-44, available from Xilinx, Inc., 2100 Logic Drive San Jose, California 95124.
Morales, Luis, "Boundary Scan in XC4000 Devices", XAPPP 017.001, Oct. 1992, pp. 1-10.

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