Programmable scan chain testing structure and method

Details Programmable scan chain testing structure and method Programmable scan chain testing structure and method

1994-04-01

1996-08-27

Trammell, James P.

Excavating

371 222, 364488, 364489, 364490, 364491, G01R 31317

Patent

active

055508430

ABSTRACT:
A circuit and method for testing Field Programmable Gate Arrays (FPGAs) comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contains an edge cell comprising a multi-input multiplexer, one of the multiplexer inputs being dedicated to receiving a signal from an adjacent cell, other of the inputs being connected to gate array input pads. A programmable control signal on the multiplexer enables the column to either receive test data from one of the gate array input pads or to connect as part of a scan chain by receiving a wrapping signal from the output logic cell of an adjacent column.

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