Programmable ROM having a reduced number of power source termina

Details Programmable ROM having a reduced number of power source termina Programmable ROM having a reduced number of power source termina

1988-07-13

1991-06-04

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

36518903, G11C 700, G11C 1140

Patent

active

050220020

ABSTRACT:
A programmable ROM is made up of a power source terminal, an internal power source voltage generator, a memory cell array, a memory cell drive circuit, and a data read-out circuit. The power source terminal receives a power source voltage of 5 V in a read mode, and a power source voltage of 12.5 V in a program mode. The internal power source voltage generator generates an internal power source voltage substantially equal to or lower than 5 V, on the basis of the power source voltage applied to the power source terminal. The memory cell array contains a plurality of memory cells. Each of the memory cells is a MOS transistor with the floating gate structure. The memory cell drive circuit is connected to the power source terminal and the internal power source voltage generator, for receiving a drive power source. The data read-out circuit is connected to the internal power source voltage generator, for receiving a drive power source. The memory drive circuit supplies a read-out voltage of 5 V to the memory cells in a read mode, and a program voltage of 12.5 V in a program mode. The data read-out circuit is driven by the 5 V power source voltage, and reads out data from the memory cells in a read mode.

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