Programmable RISC-DSP architecture

Details Programmable RISC-DSP architecture Programmable RISC-DSP architecture

1998-12-23

2001-08-28

Donaghue, Larry D. (Department: 2154)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S026000, C712S033000

Reexamination Certificate

active

06282631

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to digital signal processors and, particularly, to an architecture for digital audio signal decoders.
2. Related Art
Audio decoders used to decode encoded audio datastreams are well known. Multimedia data encoded according to a format such as MPEG-1 or MPEG-2 includes both compressed audio and video streams. Audio/video digital signal processors are used to extract separate audio and video streams from the encoded multimedia stream. Audio and video decoder components of digital signal processors then decode the extracted streams. Finally, separate audio and video processors drive audio and video output devices.
As a result, audio decoders are typically designed to handle digital signal processing (DSP) vector functions such as filtering, convolution, and transformations efficiently. In particular, DSPs typically provide special purpose hardware to perform multiply-accumulate (MAC) instructions very quickly. However, due to their special purpose architecture, such audio decoders do not perform general purpose operations such as data manipulation, conversion, and table lookup as efficiently as general purpose processors. This is because general purpose processing is typically performed by a host processor, while the audio decoder is dedicated exclusively to DSP operations.
RISC processors, on the other hand, are typically designed to handle general processing functions efficiently. This is accomplished by providing large register files or sets within the processor to allow for fast execution (e.g. one instruction per clock cycle throughput) of arithmetic operations on the data stored in the register sets. However, typical RISC processors require data stored in memory to be first loaded into the register file before executing arithmetic operations on the data. This is true even of recently developed audio decoders based on RISC architectures.
As a result, there is a need for an audio decoder capable of performing both digital signal processing and general purpose operations efficiently.
SUMMARY OF THE INVENTION
The present invention provides an audio signal processor and method of operation thereof that allows for both efficient digital signal processing and general purpose operations. This is accomplished by adding support for fast MAC (vector) operations and indirect memory addressing to a RISC-based processor to allow for efficient execution of general purpose operations such as data manipulation, conversion, and table lookup, as well as digital processing operations such as filtering, convolution, and transformation. The RISC feature of large register files is preserved, as is RISC's one instruction per cycle pipelined throughput speed.


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