Static information storage and retrieval – Read only systems – Resistive
Reexamination Certificate
1999-12-16
2001-11-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Read only systems
Resistive
C365S189070, C365S210130
Reexamination Certificate
active
06314014
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to electrically programmable memory arrays. More specifically, the present invention relates to circuitry for reading data from an array of programmable resistance elements.
BACKGROUND OF THE INVENTION
Programmable resistance memory elements formed from materials that can be programmed to exhibit at least a high or low stable ohmic state are known in the art. Such programmable resistance elements may be programmed to a high resistance state to store, for example, a logic ONE data bit or programmed to a low resistance state to store a logic ZERO data bit.
One type of material that can be used as the memory material for programmable resistance elements is phase-change material. Phase-change materials may be programmed between a first structural state where the material is generally more amorphous (less ordered) and a second structural state where the material is generally more crystalline (more ordered). The term “amorphous”, as used herein, refers to a condition which is relatively structurally less ordered or more disordered than a single crystal and has a detectable characteristic, such as high electrical resistivity. The term “crystalline”, as used herein, refers to a condition which is relatively structurally more ordered than amorphous and has lower electrical resistivity than the amorphous state.
The phase-change materials may be programmed between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. That is, the programming of such materials is not required to take place between completely amorphous and completely crystalline states but rather the material can be programmed in incremental steps reflecting (1) changes of local order, or (2) changes in volume of two or more materials having different local order so as to provide a “gray scale” represented by a multiplicity of conditions of local order spanning the spectrum between the completely amorphous and the completely crystalline states. For example, phase-change materials may be programmed between different resistive states while in crystalline form.
A volume of phase-change material may be programmed between a more ordered, low resistance state and a less ordered, high resistance state. A volume of phase-change is capable of being transformed from a high resistance state to a low resistance state in response to the input of a single pulse of energy referred to as a “set pulse”. The set pulse is sufficient to transform the volume of memory material from the high resistance state to the low resistance state. It is believed that application of a set pulse to the volume of memory material changes the local order of at least a portion of the volume of memory material. Specifically, it is believed that the set pulse is sufficient to change at least a portion of the volume of memory material from a less-ordered amorphous state to a more-ordered crystalline state.
The volume of memory material is also capable of being transformed from the low resistance state to the high resistance state in response to the input of a single pulse of energy which is referred to as a “reset pulse”. The reset pulse is sufficient to transform the volume of memory material from the low resistance state to the high resistance state. While not wishing to be bound by theory, it is believed that application of a reset pulse to the volume of memory material changes the local order of at least a portion of the volume of memory material. Specifically, it is believed that the reset pulse is sufficient to change at least a portion of the volume of memory material from a more-ordered crystalline state to a less-ordered amorphous state.
The use of phase-change materials for electronic memory applications is known in the art. Phase-change materials and electrically programmable memory elements formed from such materials are disclosed, for example, in U.S. Pat. Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046 the disclosures of which are all incorporated by reference herein. Still another example of a phase-change memory element is provided in U.S. patent application Ser. No. 09/276,273, the disclosure of which is also incorporated herein by reference.
It is important to be able to accurately read the resistance states of programmable resistance elements which are arranged in a memory array. The present invention describes an apparatus and method for accurately determining the resistance states of programmable resistance elements arranged as memory cells in a memory array. Background art circuitry is provided in U.S. Pat. No. 4,272,833 which describes a reading apparatus based upon the variation in the threshold levels of memory elements, and U.S. Pat. No. 5,883,827 which describes an apparatus using a fixed resistance element to generate reference signals. Both U.S. Pat. No. 4,272,833 and U.S. Pat. No. 5,883,827 are incorporated by reference herein.
SUMMARY OF THE INVENTION
An object of the present invention is to provide circuitry for accurately reading the resistance state of programmable resistance elements. Another objects of the present invention is to provides methods for accurately reading the resistance states of programmable resistance elements.
These and other objects are satisfied by a memory system, comprising:
one or more memory cells, each of the memory cells including a programmable resistance element programmable to at least a first resistance state and a second resistance state;
one or more reference cells, each of said reference cells including a programmable resistance element programmable to at least the first resistance state and the second resistance state; and
a comparison circuit in electrical communication with the memory cells and with the reference cells, the comparison circuit adapted to compare at least one sense signal developed by at least one of the memory cells with at least one reference signal developed by at least one of the reference cells and to provide at least one output signal in response to the comparisons.
These and other objects are satisfied by a memory system, comprising:
one or more memory cells, each of the memory cells including a programmable resistance element programmable to at least a first resistance state and a second resistance state;
one or more reference cells, each of the reference cells including a programmable resistance element programmable to at least the first resistance state and the second resistance state; and
a comparison circuit in electrical communication with the is memory cells and with the reference cells, the comparison circuit adapted to compare a sense signal developed by one of the memory cells with a reference signal developed by at least one of the reference cells and to provide an output signal in response to the comparison.
These and other objects are satisfied by a memory system, comprising:
at least a first and a second memory array, each of the arrays comprising:
one or more memory cells, each of the memory cells including a programmable resistance element programmable to at least a first resistance state and a second resistance state;
one or more reference cells, each of the reference cells including a programmable resistance element programmable to at least the first resistance state and the second resistance state; and
a comparison circuit in electrical communication with the first and second arrays, the comparison circuit adapted to compare at least one sense signal developed by at least one of the memory cells of the first array with at least one reference signal developed by at least one of the reference cells of the second array, the comparison circuit adapted to compare at least one sense signal developed by at least one of the memory cells of the second array with at least one reference signal developed by at least one of the reference cells of the first array, the comparison circuit adapted to provide at least one output signal in response to the is comparisons.
Th
Lowrey Tyler
Wicker Guy C.
Ho Hoai V.
Nelms David
Ovonyx Inc.
Schlazer Philip H.
Schumaker David W.
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