Programmable redundancy circuit

Details Programmable redundancy circuit Programmable redundancy circuit

1983-02-07

1985-12-03

Smith, Jerry

Excavating

365200, G11C 700

Patent

active

045569754

ABSTRACT:
A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder. The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

REFERENCES:
patent: 4047163 (1977-09-01), Choate et al.
patent: 4228528 (1980-10-01), Lenker et al.
patent: 4365319 (1982-12-01), Takemae
patent: 4378300 (1983-03-01), Tsang
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4422161 (1983-12-01), Kressel et al.
patent: 4441170 (1984-04-01), Folmsbee
patent: 4485459 (1984-11-01), Venkateswaran

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