Programmable read only memory with high speed differential sensi

Details Programmable read only memory with high speed differential sensi Programmable read only memory with high speed differential sensi

1999-01-27

2000-11-14

Le, Vu A.

Static information storage and retrieval

Read only systems

Semiconductive

365 94, 365103, G11C 1700

Patent

active

061478938

ABSTRACT:
A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

REFERENCES:
patent: 4773047 (1988-09-01), Uchino et al.
patent: 5394355 (1995-02-01), Uramoto et al.

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