Programmable read only memory

Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board

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Details

29580, 156644, 156653, 156657, 1566591, 357 71, 427 93, 427 94, 430317, B05D 512, B44C 122, C03C 1500, C23F 102

Patent

active

044205040

ABSTRACT:
A programmable memory element for a programmable read only memory. The programmable memory element includes a nichrome fusible link with a first metallization layer formed in contact with the nichrome fusible link. An insulating layer is formed over the first metallization layer and over a portion of the nichrome. The insulating layer is formed by first chemically vapor depositing a relatively thin layer of silicon dioxide at atmospheric pressure and then chemically vapor depositing a thicker layer of silicon nitride over the thin silicon dioxide layer, such silicon nitride layer being chemically vapor deposited in a vacuum. The layer of silicon dioxide is thin enough so that any cusps formed around the corners of the first metallization layer are relatively small. The deposition of the silicon dioxide layer is performed at atmospheric pressure and allows the silicon dioxide to provide moisture protection to the nichrome. The later deposited silicon nitride layer has sufficient thickness to provide the desired electrical insulation between a second metallization layer and the first metallization layer and the thin silicon dioxide layer provides a barrier to the silicon nitride layer so that the silicon nitride layer will not effect the resistivity of the fusible link. A via is formed in the silicon nitride layer and the underlying silicon dioxide layer to expose a portion of the first metallization layer. The second metallization layer is then deposited over the insulating layer and through the via onto the exposed portion of the first metallization layer.

REFERENCES:
patent: 3562040 (1971-02-01), Garies
patent: 3838442 (1974-09-01), Humphreys
patent: 4182781 (1980-01-01), Hooper et al.

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