Programmable pulsewidth and delay generating circuit for...

Details Programmable pulsewidth and delay generating circuit for... Programmable pulsewidth and delay generating circuit for...

2011-01-11

2011-01-11

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S231000, C365S203000, C365S204000

Reexamination Certificate

active

07869302

ABSTRACT:
A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

REFERENCES:
patent: 6279144 (2001-08-01), Henkels et al.
patent: 7630273 (2009-12-01), Suzuki
patent: 2006/0274569 (2006-12-01), Joshi et al.
patent: 2007/0201262 (2007-08-01), Joshi et al.
R. V. Joshi et al., “Variability Analysis for Sub-100 nm PD/SOI CMOS SRAM Cell”, ESSCIRC Proc.; Sep. 2004; 4 pages.
E. Leobandung et al., “High Performance 65 nm SOI Technology with Dual Stress Liner and low capacitance SRAM cell”; Symp. VLSI Tech; Jun. 2005; pp. 126-127.
P. Restle et al., “Timing Uncertainty Measurements on the Power5 Microprocessor”, ISSCC, Feb. 2004; 8 pages.
L. Chang et al., Stable SRAM Cell Design for the 32 nm Node and Beyond; Symp. VLSI Tech, 2005; pp. 128-129.

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