Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1997-09-12
2001-12-11
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C348S555000, C348S312000, C345S547000
Reexamination Certificate
active
06329982
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a pulse generating circuit of a timing generator, and more particularly to a programmable pulse generator, in which a variety of video display modes and their corresponding methods can applied to a charge coupled device (CCD) or a personal computer (PC).
BACKGROUND OF THE INVENTION
In general, there exist several methods for presenting an image in a PC-compatible format. These include a normal or high band method according to the national television system committee (hereinafter, referred to as NTSC), a normal or high band phase alternation line (hereinafter, referred to as PAL) method, the rule 601 method of international radio consultative committee (CCIR), and the VGA method.
The above methods are different from each other in their image processes. For example, the NTSC and PAL methods are compared and contrasted in the following table.
TABLE I
Method Characteristics
NTSC
PAL
the number of scans (H)
525
625
the horizontal
15.734
15.625
frequency (KHz)
the vertical frequency
59.94
50
(Hz)
picture for every
29.97
25
second (sheet)
image band (MHz)
4.2
5
audio carrier (MHz)
4.5
5.5
channel band (MHz)
6
7
chrominance sub carrier
3.579545
4.433618
(MHz)
As mentioned above, even though the plurality of image display methods are each different in broadcasting size, they can be called the PC format in view of a fact that a corresponding image can be displayed on a monitor of a PC. The MPEG technique can make any of the plurality of image processing methods applicable to the current PC.
A conventional image signal is different than an image signal compatible with the MPEG technique. Therefore, it is necessary to generate a synchronization signal adjustable to a given image processing method and there is also required a timing generator for regulating timing.
The timing generator should produce about ten clock signals, in terms of horizontal synchronization, in order to access data of the CCD, i.e., to obtain data from the CCD.
To make such a pulse, there should be designated a rising edge part and a falling edge part in each pulse. The designation operation uses about 20 reference pulses.
FIG. 1
is a diagram illustrating a conventional pulse generator
6
. Referring to
FIG. 1
, there are provided pulse production circuitry
8
, a pulse generating circuit
10
, a down counter
12
, a first NOR gate NOR
1
, and a second NOR gate NOR
2
.
In
FIG. 1
, the pulse generating circuit
10
inputs or receives twenty reference pulse signals P
1
-P
20
from the pulse production circuity
8
, a first discriminating signal NTPAL for discriminating the NTSC method from the PAL method, and a second discriminating signal NORHI for discriminating a normal band mode or a high band mode. It compounds the signals according to each state of the discriminating signals to thereby output five mode decision pulse signals DD
1
-DD
5
.
The down counter
12
of
FIG. 1
inputs or receives the mode decision pulse signals DD
1
-DD
5
from the pulse generating circuit
10
, and down-counts the signals by a control signal from the second NOR gate NOR
2
(to be discussed further below). The first NOR gate NOR
1
inputs or receives signals from nodes within the down counter
12
and outputs a logical NOR combination of these signals as the signal MSC. The second NOR gate NOR
2
inputs or receives the MSC signal and a horizontal synchronization detection signal HD and outputs a logical NOR combination of these signals to the down counter
12
as a control signal thereof.
The pulse generating circuit
10
according to the conventional art combines the reference pulse signals P
1
-P
20
differently according to the normal or high band mode of the NTSC method or the normal or high band mode of the PAL method, i.e., according to the different logic states of the first and second discriminating signals NTPAL and NORHI. The conventional art has pulse production circuits
8
and pulse generating circuits
10
corresponding to each of the four modes, respectively.
The pulse generator
6
according to the conventional art is intended to mux and set the reference pulse signals. The output signal MSC from the first NOR gate NOR
1
is provided to the second NOR gate NOR
2
through a feed-back connection.
The mode decision pulse signals DD-DD
5
are inputted to the down counter
12
. The down counter
12
subtracts a counting value from loading values by
1
every clock pulse, and finally outputs a counting value “0”. Here, if data outputted from the down counter
12
are all “0”, the output signal of the first NOR gate is at the high state.
The pulse generator according to the conventional art is applied to only the normal or high band mode of the NTSC method, or the normal or high band mode of the PAL method. The number of pulses supplied as the reference pulse signals is fixed as
20
, i.e., P
1
-P
20
. Thus, in case that the size of the CCD, or the number of the pixels of the CCD is changed, and in case that a new method should be applied to the pulse generator, there arises a problem in that it is difficult to apply the new method to the pulse generator according to the conventional art.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a pulse generator capable of applying a variety of methods, corresponding to a variety of video methods, to a charge coupled device CCD or a monitor of a personal computer PC.
These and other objects of the present invention are achieved by providing a programmable pulse generator, and method embodied therein, for video system, the programmable pulse generator comprising: a multi-pulse circuit selectively outputting one of a plurality of predetermined mode decision signal state sets for a given one of a plurality of video modes according to a selection signal; and selection logic for generating said selection signal for said multi-pulse circuit. The programmable pulse generator can also include a memory for storing said plurality of predetermined mode decision signal state sets for said plurality of video modes; and a controller for providing one of said pluralities of said state sets to said multi-pulse circuit according to said given video mode.
The multi-pulse circuit of the present invention can include a shift register bank having a plurality of serially connected shift registers, each shift register latching one of said state sets, wherein a given one of said shift registers is connected to said selection logic in such a way that said selection signal is generated by said selection logic as function of the state set in said given shift register. It can also include a controllable switch for selectively connecting the last shift register in said shift register bank to a first shift register in said shift register bank to form a feed back loop such that the state sets in said shift register bank can be recirculated therethrough. The controllable switch is controlled by a controller to select either the output of said given shift register or one of said pluralities of said state sets according to said given video mode.
The foregoing and other objectives of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 4907089 (1990-03-01), Yamaguchi et al.
patent: 5124796 (1992-06-01), Maki
patent: 5856818 (1999-01-01), Oh et al.
patent: 5894299 (1999-04-01), Tsuchiya et al.
patent: 5990857 (1999-11-01), Kubota et al.
Hjerpe Richard
Hynix / Semiconductor Inc.
Nguyen Frances
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