Programmable power consumption pipeline analog-to-digital...

Details Programmable power consumption pipeline analog-to-digital... Programmable power consumption pipeline analog-to-digital...

2000-08-21

2002-01-22

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S163000

Reexamination Certificate

active

06340944

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to analog-to-digital converters, and in particular to the reduction of power consumption for such circuits.
Portable, battery powered electronics are constantly optimizing circuitry to minimize power consumption. The goal in minimizing power consumption is to extend battery life. Many portable electronic devices require mixed-mode analog-to-digital converter (ADC) integrated circuits. Examples of these devices include video devices such as digital still cameras (DSC) and camcorders. These video devices are a particularly challenging design task because of the fidelity and high speed required in video processing. Typically, increased power consumption is required for the ADC in higher speed applications, such as video, to meet these design constraints. The invention described herein optimizes power consumption with a video application. The present invention provides an ADC design and methodology that minimizes power consumption for typical use of digital still cameras and camcorders. For the sake of simplicity, we will define two modes of user operation:
1. Recording mode.
2. Viewfinder mode.
Recording Mode
Mode 1, recording mode, is self descriptive. The user intends to record video during this time. A camcorder in this mode would be recording video to a storage media. A digital still camera would be recording a picture to storage media. These recording events are assumed to require full accuracy from the circuitry in use. For example, if the ADC had 12-bit capability, all 12 bits would be used. This assumption of performance is based on the user's expectation of the best image quality possible.
Viewfinder Mode
Mode 2, viewfinder mode, is a preview for playback mode. The user is typically viewing video on a liquid crystal display (LCD) during this mode. Users of DSCs and camcorders spend considerable time viewing video on the LCD in this mode. During this mode users are not recording video. This mode is further divided in two subsets of use: playback and preview.
Playback is the event of recalling video from a media to an LCD or NTSC output. It does not involve recording of video. The ADC circuitry in this more can simply be powered down and not used.
Preview is the event where ADC power is optimized in the present invention. Preview is the event of viewing video on an LCD, for example, but not recoding to a storage media. Examples of this event include framing a picture before it is taken and framing a subject in a camcorder prior to recording. ADC circuitry is used in this mode but storage media is not written to or accessed. The ADC in this mode can be optimized for power consumption. Users spend significant time in this mode of operation by comparison to other modes. In this preview mode it is assumed that less than best possible image performance (image performance during recording) is acceptable. An LCD, for example, has an 8-bit digital interface or 6-bit accurate NTSC interface. LCD preview performance in this mode is therefore limited to 6 or 8-bit system performance. An ADC digitizing video to a 12-bit level would therefore not need to be accurate to greater than 6 to 8 bits in the system. The ADC can utilize a lower resolution mode to match needed system performance and save power consumption.
SUMMARY OF THE INVENTION
The present invention provides an analog-to-digital converter which has a low resolution and high resolution mode. In response to the low resolution mode signal, a switching circuit selects only certain of the digital bit outputs.
In one embodiment, the analog-to-digital converter is a pipelined circuit with a number of stages. In response to the low resolution mode, a number of the stages are bypassed, so that only the needed stages for the smaller number of bits are used. The stages that are bypassed are preferably powered down, but not completely. By maintaining a small amount of bias current to the bypassed stages, they can quickly respond when a switch is made back to full resolution mode.
In one preferred embodiment, the output bits are also switched so that they are shifted over from the LSB positions to the MSB positions. In another aspect of this embodiment, a latency matching circuit, such as D-latches are used to maintain an equal latency for both high resolution and low resolution modes. Thus, the D-latches provide the latency that would otherwise have been provided by the bypassed stages.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5898396 (1999-04-01), Shimomura et al.

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