Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-04-19
2011-04-19
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S016000
Reexamination Certificate
active
07930517
ABSTRACT:
An array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.
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Coleman Eric
Connolly Bove & Lodge & Hutz LLP
Wave Semiconductor, Inc.
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