Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2006-11-17
2008-10-28
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S011000, C331S016000, C331S025000, C331S044000
Reexamination Certificate
active
07443250
ABSTRACT:
A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.
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Notice of Allowance mailed May 14, 2008 in U.S. Appl. No. 11/537,082, filed Sep. 29, 2006, entitled, “Technique for Switching Between Input Clocks in a Phase-Locked Loop,” and naming inventors Ronald Hulfachor, Srisai Seethamraju , and Shailesh Chitnis, 6 pages.
Anker William J.
Hulfachor Ronald B.
Juhn Richard J.
Seethamraju Srisai R.
Mis David
Silicon Laboratories Inc.
Zagorin O'Brien Graham LLP
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