Programmable phase locked-loop filter architecture for a...

Details Programmable phase locked-loop filter architecture for a... Programmable phase locked-loop filter architecture for a...

2000-09-20

2003-10-07

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Unwanted signal suppression

C327S308000

Reexamination Certificate

active

06630860

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to integrated circuit (IC) active loop filter circuitry and, more particularly, to a filter network that can be programmed to operate over multiple bandwidth ranges in a phase locked-loop system.
2. Description of the Related Art
Phase locked loop circuits, including active filters, are used in communication systems and also as part of larger digital system applications such as clock de-skewing, clock synchronization, high speed serial transmission, and clock recovery. The challenges of the complicated larger systems configured from integrated circuits include variable supply noise frequency spurs (system dependent), variable bandwidth requirements (system application dependent), and reliable operation of the phase locked-loop systems under the stringent requirements. Thus, the challenge is to design a phase-locked loop (PLL) that is configured to satisfy the application dependent bandwidth requirements, as well as variable power supply noise frequency requirements.
FIG. 1
is a schematic block diagram illustrating a generic PLL circuit
10
using an active filter architecture (prior art). An active filter
12
is a key component of the loop. The bandwidth (BW) of the PLL is given by the following equation:
 
PLL BW=
(
K
PD
/2&pgr;)*(
K
V
/N
)*(
R
2
/
R
1
)*
A
loop damping=0.5*(
sqrt{K
PD
**(
K
V
/N
)*
A
*(
R
2
2
*C
)/
R
1
}
where K
PD
and K
V
are phase detector and VCO gain parameters, respectively. A is the external attenuation factor of the PLL. Typically, A=1 for on-chip PLL implementations. R
1
, R
2
, and C are components of the active filter
12
.
FIG. 2
is a schematic diagram illustrating the active filter
12
of the PLL of
FIG. 1
(prior art). The bandwidth and stability parameters of the PLL are determined by the values of R
1
(
16
), R
2
(
18
), C (
20
), and attenuation factor A, which is defined by the ratio of R
4
(
24
) to R
3
(
22
). For discrete integrated circuit applications, these tuning components have been conventionally located external to the IC, on the printed circuit board (PCB). However, these components take up PCB real estate and their exposure can lead to the injection of noise at critical circuit nodes, which degrades performance. Prior art on-chip integrated circuit PLL circuits are also known. However, due to the limited range of IC internal tuning components, a corresponding limited range of PLL bandwidths are available. Other schemes use multiplexor (MUX) circuits to provide a great range of tuning components, but the multiplexor circuit connections are necessarily numerous, permitting the injection of noise into the more sensitive nodes of the PLL system. Other designs provide PLL bandwidth ranges by providing an IC with parallel tuning circuits. The limited number of node connections in the chosen circuit reduces the noise injection problem, but space and power consumption on the IC is wasted.
Parallel circuits of duplicate parts are required, where each parallel circuit contains its own amplifier, tuning components, and oscillator.
It would be advantageous if an IC could be devised for configuring PLL bandwidth ranges with the minimum number of internal IC components. Likewise, it would desirable if the bandwidth ranges could be selected with the minimum number of instructions, such as with a user programmable configuration register.
It would be advantageous if the above-mentioned bandwidth range selectable IC could be devised to optionally operate with external components to provide configurable bandwidth ranges.
SUMMARY OF THE INVENTION
Accordingly, a programmable active filter architecture is provided for IC designs such as phase-locked loop systems. The invention represents a significant improvement over conventional active filter implementations in terms of the flexibility offered in the selection of the desired range (low or high) bandwidth and desired filter mode (external or internal implementation). The bandwidth ranges are available without having to implement a system of different selectable loops. The invention describes the circuit implementation details of the active filter components, loop stability considerations, programmable features for selecting the bandwidth range (low or high) and filter mode (external or internal).
More specifically, a PLL active filter integrated circuit with selectable bandwidth ranges is provided. The PLL active filter comprises an amplifier and a filter network. The filter network is coupled to the amplifier and supplies a plurality of PLL bandwidth ranges in response to the bandwidth range commands.
For example, when the filter network accepts an external mode, low bandwidth range command, the filter network supplies a large value of R
1
resistance, a small value of R
2
resistance, and a large Cl capacitance in parallel to the R
2
resistance. An external capacitor can also be selectively connected between the filter network and the amplifier output for improved damping. When the filter network accepts an external mode, high bandwidth command, the filter network supplies a low value of R
1
resistance, a large value of R
2
resistance, and a small C
1
capacitance in parallel to the R
2
resistance. Again, the external capacitor can be selectively added to the filter to modify the damping factor. The filter network also has an internal mode, high bandwidth range command. Actually, there are a plurality of internal mode, high bandwidth range commands, where each specific command corresponds to a selected value of R
1
resistance. The internal mode, high bandwidth range commands also select a (fixed) low value of R
2
resistance and a (fixed) large value of C
1
capacitance in parallel to the R
2
resistance.


REFERENCES:
patent: 4733205 (1988-03-01), Hughes
patent: 4785253 (1988-11-01), Hughes
patent: 4857778 (1989-08-01), Hague
patent: 5113116 (1992-05-01), Wilson
patent: 5272452 (1993-12-01), Adachi et al.
patent: 5278478 (1994-01-01), Moody et al.
patent: 5317217 (1994-05-01), Rieger et al.
patent: 5331218 (1994-07-01), Moody et al.
patent: 5345119 (1994-09-01), Khoury
patent: 5392456 (1995-02-01), Mitomo et al.
patent: 6072360 (2000-06-01), McCullough
patent: 6366161 (2002-04-01), Koazechi

Affiliated with

Also associated with

Rating

Programmable phase locked-loop filter architecture for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable phase locked-loop filter architecture for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable phase locked-loop filter architecture for a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3172321