Programmable peripheral processing controller

Details Programmable peripheral processing controller Programmable peripheral processing controller

1980-12-29

1983-07-19

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1300

Patent

active

043947344

ABSTRACT:
A peripheral processing controller controls access to a peripheral memory by specialized peripheral devices. The specialized peripheral devices process all of the data independently of a central processor that simply supervises the system. The controller uses Memory Address Registers (MARs) to control the access to the memory by the peripheral devices. Each peripheral device selects a MAR, and each MAR includes a mode register. The start address and mode are set in each MAR by the supervising central processor. Also, each peripheral device is set by the processor to select a MAR. When the controller grants each peripheral device access to the peripheral memory, the peripheral device uses whatever mode and starting address has been initialized for the MAR selected by the device. Each time the device accesses the memory, the address in the MAR is incremented so the MAR is ready for the next access. In this way, a peripheral device will advance through a block of memory space. The mode is used to specify the end-of-block (EOB) condition for the block of memory space that the peripheral device is working with. The EOB may be based on the number of accesses by a device to the memory or it may be based on particular memory addresses.

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