Programmable pattern generation for dynamic bus signal...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C716S030000, C716S030000, C703S002000, C703S003000, C703S015000, C703S016000, C703S019000, C703S022000

Reexamination Certificate

active

10379977

ABSTRACT:
A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.

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Lai et al., “Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses” IEEE 2001 p. 204-209.

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