Programmable parity checking and comparison circuit

Excavating

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371 671, 39518204, 39518505, G06F 1100

Patent

active

057198896

ABSTRACT:
A programmable parity circuit for a memory array includes at least one programmably selectable set of inputs arranged such that the circuit can be programmably configured to perform odd or even parity operations for data stored or to be stored in the memory array or to alternatively perform non-parity bit-wise comparisons for circuits outside the memory array. Provision is made for a variety of routing configurations.

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S. J.Hong, et al., "Array Logic Implementation of Decoder Check", IBM Technical Disclosure Bulletin, vol. 14, No. 8, Jan. 1972, p. 2362.
J. W. Jones, "Shared Macros and Facilities In Programmable Logic Arrays", IBM Technical Disclosure Bulletin, vol. 18, No. 3, Aug. 1975, pp. 823-825.

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