Programmable non-integer fractional divider

Details Programmable non-integer fractional divider Programmable non-integer fractional divider

2000-10-20

2004-06-08

Chaki, Kakali (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06748408

ABSTRACT:

RELATED PATENT APPLICATION
This application claims priority from European patent application number 99480097.7, filed Oct. 21, 1999, which is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present invention relates to dividers, and more particularly to a programmable non-integer fractional divider.
BACKGROUND ART
Phase-locked loops (PLLs) are used in a wide variety of applications in semiconductor devices. For example, PLLs are used in clock generators, frequency multipliers, frequency synthesizers, servo systems in disk drives and more recently in wireless networks. Naturally, in all of these and other applications the accuracy and reliability of the PLL is of critical importance.
A common phase-locked loop comprises a phase comparator, a charge pump, a filter, a voltage-controlled oscillator (VCO) and a feedback divider. The general operation of PLL's is well known, so only a brief explanation will be given. The phase comparator compares a reference input signal ‘Fq’ from a quartz to a feedback signal from the feedback divider. Depending upon the phase difference between the input signal and feedback signal, the phase comparator drives the charge pump. The output of the charge pump is filtered by the filter, and is used to drive the VCO. The VCO comprises a voltage-to-current converter and a current controlled oscillator. Thus, the VCO receives a voltage at its input and outputs a signal with a frequency proportional to that signal. Of course, those skilled in the art will recognize that this description of the VCO is essentially arbitrary and that the VCO could be illustrated as separate voltage-to-current converter and current-controlled oscillator rather than as a single element. The output of VCO fed back through feedback divider to phase comparator. The feedback divider divides down the VCO output signal frequency ‘Fvco’ to match the quartz input signal frequency ‘Fq’ so they can be phase compared.
The frequency at which the phase-locked loop operates is dependent upon the frequency of the VCO and the amount of division by the feedback divider. To change the VCO output frequency ‘Fvco’, these elements must be adjusted. Typically, the frequency at the input of the feedback divider ‘Fvco’ is divided by an integer ratio ‘N’ in the way that Fout=Fvco/N, where N is the integer value.
In some circuits, to improve the granularity of the system the quartz input signal frequency ‘Fq’ is also divided by an integer ratio ‘B’ before entering the phase comparator. The two frequencies at the input of the comparator are then related according to the formula:
Fvco
N
=
Fq
B
which may be rewritten as:
Fvco
=
Fq
×
N
B
It is readily understood that a high granularity may be obtained by increasing the value of ‘B’.
Unfortunately the higher the value of ‘B’ is, the lower the bandwidth is. Therefore, with the known integer dividers, a tradeoff is to be found between granularity and bandwidth values.
One obvious solution to have a high bandwidth is to have a value of ‘B’ equal to ‘1’, but in such case the granularity is limited to the value of Fq.
Non-integer values for ‘N’ are a solution for reducing the incremental performance granularity normally taken for integer ratios. However, current circuits for producing such non-integer ratios are limited to a few non-integer values. Such a prior art circuit for producing a non-integer ratio is disclosed in U.S. Pat. No. 4,891,774 from Bradley in which a dual modulus fractional divider having a dual modulus prescaler is coupled to a programmable divider. Latches and a full adder are provided for programming the programming divider with a modulus A, a modulus B, a modulus (A−1) and a modulus (B+1). A rate multiplier controls the adder to provide the desired resolution of the divider.
Therefore, there exist a need to provide an improved PLL that can operate on a wide bandwidth while having a high granularity.
The invention can be implemented in any PLL requiring a high granularity and a high frequency bandwidth, whereas, classical PLL designs allow users to trade-off between high granularity
arrow bandwidth or wide bandwidth/weak granularity. In application, the invention is suitable to operate on a bandwidth range of hundred of MHz with a granularity of hundred of kHz.
SUMMARY OF THE INVENTION
The present invention solves the foregoing need by using a VCO generating a plurality of out of phase clock signals coupled to a non-integer fractional divider. According to the present invention, the fractional divider comprises means for dividing a reference clock signal ‘Fvco’ having a period ‘P’ by a non-integer ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals ‘Fvco_
0
to Fvco_(n−1)’ issued from the reference clock signal ‘Fvco’, and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals ‘Fvco_
0
to Fvco_(n−1)’. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio ‘K’. The selected clock signals are combined into combining means responsive to the receiving means to output a divided clock signal ‘Fvco/K’ such that the enabling time of each selected clock signal is respectively representative of the duration of the low level and the high level of the divided clock signal. The appropriate selection of the first and second clock signals is repeated at each clock cycle according to a general formula wherein ‘K’ is decomposed into integer and non-integer values.


REFERENCES:
patent: 4241408 (1980-12-01), Gross
patent: 5038117 (1991-08-01), Miller
patent: 5287296 (1994-02-01), Bays et al.
patent: 5371765 (1994-12-01), Guilford
patent: 5761101 (1998-06-01), Erhage
patent: 5999581 (1999-12-01), Bellaouar et al.
patent: 6157694 (2000-12-01), Larsson
patent: 6219397 (2001-04-01), Park
patent: 6356123 (2002-03-01), Lee et al.
patent: 6441655 (2002-08-01), Fallahi et al.
patent: 6501336 (2002-12-01), Kim et al.

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