Programmable non-integer fractional divider

Details Programmable non-integer fractional divider Programmable non-integer fractional divider

2001-08-23

2004-10-19

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Pulse repetition rate

C327S115000, C377S048000

Reexamination Certificate

active

06807552

ABSTRACT:

TECHNICAL FIELD
The present invention relates to dividers, and more particularly to a programmable non-integer fractional divider.
BACKGROUND ART
Phase-locked loops (PLLs) are used in a wide variety of applications in semiconductor devices. For example, PLLs are used in clock generators, frequency multipliers, frequency synthesizers, servo systems in disk drives and more recently in wireless networks. Naturally, in all of these and other applications the accuracy and reliability of the PLL is of critical importance.
A common phase-locked loop comprises a phase comparator, a charge pump, a filter, a voltage-controlled oscillator (VCO) and a feedback divider. The general operation of PLL's is well known, so only a brief explanation will be given. The phase comparator compares a reference input signal ‘Fq’ from a quartz to a feedback signal from the feedback divider. Depending upon the phase difference between the input signal and feedback signal, the phase comparator drives the charge pump. The output of the charge pump is filtered by the filter, and is used to drive the VCO. The VCO comprises a voltage-to-current converter and a current controlled oscillator. Thus, the VCO receives a voltage at its input and outputs a signal with a frequency proportional to that signal. Of course, those skilled in the art will recognize that this description of the VCO is essentially arbitrary and that the VCO could be illustrated as separate voltage-to-current converter and current-controlled oscillator rather than as a single element. The output of VCO fed back through feedback divider to phase comparator. The feedback divider divides down the VCO output signal frequency ‘Fvco’ to match the quartz input signal frequency ‘Fq’ so they can be phase compared.
The frequency at which the phase-locked loop operates is dependent upon the frequency of the VCO and the amount of division by the feedback divider. To change the VCO output frequency ‘Fvco’, these elements must be adjusted. Typically, the frequency at the input of the feedback divider ‘Fvco’ is divided by an integer ratio ‘N’ in the way that
F
out
=
F
vco
N
,
where N is the integer value.
In some circuits, to improve the granularity of the system the quartz input signal frequency ‘Fq’ is also divided by an integer ratio ‘B’ before entering the phase comparator. The two frequencies at the input of the comparator are then related according to the formula:
F
vco
N
=
Fq
B
which may be rewritten as:
Fvco
=
Fq
×
N
B
It is readily understood that a high granularity may be obtained by increasing the value of ‘B’.
Unfortunately the higher the value of ‘B’ is, the lower the PLL bandwidth ‘BW
pll
’ is, according to the formula:
Bwpll
=
Fq
÷
10
×
1
B
Therefore, with the known integer dividers, a tradeoff is to be found between granularity and PLL bandwidth values.
One obvious solution to have a high PLL bandwidth is to have a value of ‘B’ equal to ‘1’, but in such case the granularity is limited to the value of Fq.
Non-integer values for ‘N’ are a solution for reducing the incremental performance granularity normally taken for integer ratios.
Such a prior art circuit for producing a non-integer ratio is disclosed in U.S. Pat. No. 4,891,774 from Bradley in which a dual modulus fractional divider having a dual modulus prescaler is coupled to a programmable divider. Latches and a full adder are provided for programming the programming divider with a modulus A, a modulus B, a modulus (A−1) and a modulus (B+1). A rate multiplier controls the adder to provide the desired resolution of the divider.
However, those existing circuits for producing non-integer ratios are limited to a few non-integer values.
Thus, the prior art PLL designs only allow the users to trade-off between ‘a high granularity with a narrow bandwidth’ or ‘a wide bandwidth with a weak granularity’.
U.S. application Ser. No. 09/693057 from the assignee, discloses a programmable non-integer fractional divider which uses the ‘N’ internal phases of the VCO as inputs, and delivers an output ‘Fdiv’ whose frequency is a non integer sub-multiple of the VCO frequency ‘Fvco’. This solution is well suited for an implementation based on a high level language description. Unfortunately, the use of a high level language to implement and synthesize the different logic blocks of this programmable non-integer fractional divider is not well suited when high frequency performance and high timing accuracy are required. This programmable non-integer fractional divider is able to operate at a maximum frequency of 300 MHz under worst case conditions of a 0.25 &mgr;m CMOS technology.
Moreover, this programmable fractional divider is designed to delivered a 50% duty cycle. This feature is obtained by the use of an ‘even and odd’ integer counter and an ‘even and odd’ non-integer incrementer.
However, in some PLL applications the need to get a divided frequency with a 50% duty cycle to feed the phase frequency detector (PFD) is not mandatory. Indeed, all the PFD's work on one edge (either the rising or the falling edge) and do not care of the opposite one (respectively the falling or rising one). Consequently, the PFD's do not required a 50% duty cycle.
Therefore, there exist a need to provide an improved PLL that can operate on a wide bandwidth while having a high granularity, and that can operate on various duty cycles.
SUMMARY OF THE INVENTION
The present invention solves the foregoing need by using a VCO generating a plurality of out-of-phase clock signals coupled to a non-integer fractional divider. According to the present invention, the fractional divider comprises means for dividing a reference clock signal ‘Fvco’ having a period ‘P’ by a non-integer ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals ‘Fvco
—
0 to Fvco_(n−1)’ issued from the reference clock signal ‘Fvco’, and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals ‘Fvco
—
0 to Fvco_(n−1)’. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio ‘K’. The selected clock signals are combined into combining means responsive to the receiving means to output a divided clock signal ‘Fvco/K’. The appropriate selection of the first and second clock signals is repeated at each clock cycle according to a general formula wherein ‘K’ is the summation of an integer I, and a decimal X values:
K=I+X
The output duty cycle is equal to:
Duty_cycle
=
1
K
In a preferred embodiment, the circuits are full custom design in order to get a very high frequency performance. As a result, in operation the fractional divider of the present invention exhibits a ×3 performance improvement compared to previous approach which means an operating frequency of 900 MHz under worst case conditions of a 0.25 &mgr;m CMOS technology.
In application, the invention is suitable to operate on a bandwidth range of hundred of MHz with a granularity of hundred of kHz.
The non-integer fractional divider of the present invention thus enables:
i) a drastically simplification of the overall design, and
ii) a drastically improvement of the maximum frequency of operation as compared to the prior art solutions by providing:
a circuitry which reduces the total number of devices used; and
a new state machine algorithm which simplifies the control logic circuit.
Preferably, the system of the invention is a non-integer fractional divider for dividing a reference clock signal ‘Fvco’ of period ‘P’ by a non-integer ratio ‘K’, the non-integer ratio being decomposed into an integer part ‘I’ and a non-integer part ‘X’. The non-integer fractional divider comprising:
first and second receiving means for respectively receiving an identical plurality ‘N’ of clock signals ‘Fvco
—
0 to Fvco_(N−1)’, ea

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